Changhwan Shin

Study of Random Dopant Fluctuation Effects in Germanium-Source Tunnel FETs

The effects of random dopant fluctuations (RDFs) on the performance of Germanium-source tunnel field-effect transistors (TFETs) is studied using 3-D device simulation. The RDF in the source region is found to have the most impact on threshold voltage variation (σ<i>V</i>_TH) if the source is moderately doped (10¹⁹ cm^-3) such that vertical tunneling within the source is dominant. If the source is heavily doped (10²⁰ cm^-3) such that lateral tunneling from the source to the channel is dominant, the impact of RDF in the channel region is also significant. RDF-induced threshold voltage variation (σ<i>V</i>_TH) for an optimally designed Ge-source TFET is relatively modest (σ<i>V</i>_TH <; 20 mV at <i>Lg</i> = 30 nm), compared with a MOSFET of similar gate length. Supply voltage scaling is not beneficial for reducing TFET σ<i>V</i>_TH.

Tri-Gate Bulk MOSFET Design for CMOS Scaling to the End of the Roadmap

A tri-gate bulk MOSFET design utilizing a low-aspect-ratio channel is proposed to provide an evolutionary pathway for CMOS scaling to the end of the roadmap. 3-D device simulations indicate that this design offers the advantages of a multi-gate FET (reduced variability in performance and improved scalability) together with the advantages of a conventional planar MOSFET (low substrate cost and capability for dynamic threshold-voltage control).

Study of Random-Dopant-Fluctuation (RDF) Effects for the Trigate Bulk MOSFET

A study of random-dopant-fluctuation (RDF) effects on the trigate bulk MOSFET versus the planar bulk MOSFET is performed via atomistic 3D device simulation for devices with a 20 nm gate length. For identical nominal body and source/drain doping profiles and layout width, the trigate bulk MOSFET shows less threshold voltage (Vth) lowering and variation. RDF effects are found to be caused primarily by body RDF. The trigate bulk MOSFET offers a new method of VTH adjustment, via tuning of the retrograde body doping depth, to mitigate tradeoffs in VTH variation and short-channel effect control.

Feedback FET: A novel transistor exhibiting steep switching behavior at low bias voltages

A novel transistor design which utilizes positive feedback to achieve steep switching behavior is proposed and demonstrated. The feedback (FB) FET exhibits very low subthreshold swing (~2 mV/dec) and high ION/IOFF ratio (~108) to allow for significant reductions in gate voltage swing (to below 0.5V). It is a new candidate to replace the MOSFET for future low-power electronic devices.

Variation Study of the Planar Ground-Plane Bulk MOSFET, SOI FinFET, and Trigate Bulk MOSFET Designs

The impact of systematic and random variations on transistor performance is investigated for the trigate bulk MOSFET, the planar ground-plane bulk MOSFET, and SOI FinFET. The results indicate that the trigate bulk MOSFET design is least sensitive to process-induced variations and offers the best nominal performance, as compared with the planar ground-plane bulk MOSFET and SOI FinFET.

Performance and Area Scaling Benefits of FD-SOI Technology for 6-T SRAM Cells at the 22-nm Node

The performance and threshold voltage variability of fully depleted silicon-on-insulator (FD-SOI) MOSFETs are compared against those of conventional bulk MOSFETs via 3-D device simulation with atomistic doping profiles. Compact (analytical) modeling is then used to estimate six-transistor SRAM cell performance metrics (i.e., read and write margins, and read current) at the 22 nm CMOS technology node. The dependences of these metrics on cell ratio, pull-up ratio, and operating voltage are analyzed for FD-SOI versus bulk SRAM cells. Iso-area and iso-yield comparisons are then made to determine the yield and cell-area benefits of FD-SOI technology, respectively. Finally, the minimum operating voltages required for FD-SOI and bulk SRAM cells to meet the six-sigma yield requirement are compared.

Design Optimization of Multigate Bulk MOSFETs

The design optimization of multigate bulk MOSFET structures is investigated for sub-20-nm gate lengths. Three-dimensional device simulations were used to optimize device design parameters such as the retrograde channel doping profile, as well as the length, width, and height of the gated channel region. Compared with the FinFET design, the results indicate that the tri-gate MOSFET design is promising for continued bulk-Si CMOS transistor scaling, because it can achieve similar on-state current performance and intrinsic delay [for the same channel stripe pitch (SP)] at a lower height/width aspect ratio (0.8 versus 2.17) and less aggressive retrograde channel doping gradient for improved manufacturability. Only by increasing the height of the channel region and/or reducing the channel SP can the FinFET bulk MOSFET design achieve better delay, but at the cost of reduced manufacturability.

Analysis of the relationship between random telegraph signal and negative bias temperature instability

Random telegraph signal (RTS) is shown to be an intrinsic component of the shift in MOSFET threshold voltage (Vth) due to bias temperature instability (BTI). This is done by starting from a well-known model for negative BTI (NBTI), to derive the formula for RTS-induced Vth shift. Based on this analysis, RTS simply contributes an offset in NBTI degradation, with an acceleration factor that is dependent on the gate voltage and temperature. This is verified by 3-dimensional (3-D) device simulations and measurements of 45 nm-node bulk-Si PMOS transistors. It has an important implication for design of robust SRAM arrays in the future: design margin for RTS should not be simply added, because it is already partially accounted for within the design margin for NBTI degradation.

Performance and Yield Benefits of Quasi-Planar Bulk CMOS Technology for 6-T SRAM at the 22-nm Node

The performance and threshold voltage variability of quasi-planar bulk MOSFETs are compared against those of conventional bulk MOSFETs, via three-dimensional (3-D) device simulations with gate line-edge roughness and atomistic doping profiles, at 25 nm gate length. The nominal performance of six transistor (6-T) SRAM cells is studied via 3-D simulation of full cell structures. Compact (analytical) modeling is used to estimate SRAM cell yields. As compared to conventional bulk CMOS technology, quasi-planar bulk CMOS technology provides for enhanced SRAM cell performance and yield, and hence facilitates reductions in cell area and operating voltage. It also enables a notchless 6-T SRAM cell design which is advantageous for improved lithographic printability and either smaller area or lower standby power, and is projected to achieve 6-sigma cell yields at operating voltages down to ~0.8 V.

SRAM yield enhancement with thin-BOX FD-SOI

The performance and yield of 6-T SRAM cells implemented in thin-BOX FD-SOI technology vs. bulk technology are compared via 3-dimensional (3D) atomistic process and device simulations and analytical modeling for SRAM yield estimation. Performance is enhanced due to the elimination of channel dopants, and variation due to gate-LER and RDF are suppressed, for FD-SOI technology. For the same cell area (∼0.07µm2), comparable SNM can be achieved with 30% higher write current, and SRAM yield is enhanced by ≫2 sigma.