Chanho Lee

Traffic sign detection and identification using SURF algorithm and GPGPU

Traffic sign identification is one of the key components of the Driver Assistant Systems (DAS). It can provide important information for safety driving. In this paper, we propose a method for traffic sign detection and identification. First, potential traffic signs are segmented by color threshold, and a polygon approximation algorithm is used to detect appropriate polygons. The potential signs are compared with the template signs in the database using SURF feature matching method. In the identification step, we apply the SURF algorithm for a CPU only system and a CPU with GPGPU system. Experiment results show that our method works robustly and efficiently for the selected data.

Design of an H.264 decoder with variable pipeline and smart bus arbiter

H.264 video coding standard is widely used due to the high compression rate and quality. H.264 decoders usually have pipeline architecture by a macroblock or a 4 × 4 sub-block. The period of the pipeline is usually fixed to guarantee the operation in the worst case which results in many idle cycles and higher data bandwidth. We propose variable pipeline architecture for H.264 decoders for efficient decoding and lower the requirement of the bandwidth for the memory bus. A smart bus arbiter is introduced to adjust the priority adaptively so that the access to a reference memory does not degrade the performance of the decoding pipeline. An H.264 decoder is designed and implemented using the proposed architecture to verify the operation using an FPGA.

Design of a motion compensation unit for H.264 decoder using 2-dimensional circular register files

H.264 video coding standard is widely used due to the high compression rate and quality. The motion compensation is the most time-consuming and complex unit in the H.264 decoder. The performance of the motion compensation is determined by the calculation of pixel interpolation and management of the reference pixels. The reference pixels read from external memory and efficient memory management for data reuse is necessary. We propose the architecture of a motion compensation for H.264 decoders. It is composed of 2-dimensional circular register files, a motion vector predictor and interpolators with dual-channel pipelined processing elements. The processing elements can interpolate integer-, half- and quarter-pixel data. The 2-dimensional circular register files reuse reference pixel data as much as possible, and feed reference pixel data to interpolators without any latency and complex logic circuits. The motion compensation unit has dual processing pipelines for luminance and chroma data. We design a motion compensation unit for the baseline profile using Verilog-HDL.

Design of a geometry engine for mobile 3D graphics

Recently, portable devices employ applications using 3D graphics such as 3D games and 3D navigations. The portable devices require small area and low power consumption. We propose architecture for a geometry engine for 3D mobile graphics. The proposed geometry engine consists of a transformation engine and a lighting engine. The transformation engine employs two step culling scheme which reduces the complexity of pipelines. The lighting engine has variable pipelines depending on the lighting effects and the number of lighting sources. The geometry engine supports the 32 bit single precision format of the IEEE-754 standard and the reduced 24 bit floating point format for mobile environment. We design a geometry engine based on the proposed architecture using Verilog-HDL and synthesized it using a 0.25 um CMOS standard cell library at 100 MHz. It is verified by simulation and implementing on an FPGA.

Design of eMMC controller with multiple channels

Embedded multimedia card (eMMC) is expected to replace secure digital (SD) card which is widely used for external memory and to be used widely in the embedded systems due to the improved performance and package. In this paper, we propose architecture of eMMC controller with multiple channels. It is connected to a host system using an AXI master interface for data transfer and an APB slave interface for writing command and reading responses and status. The interface for eMMC devices has multiple channels for multiple devices and each channel can be enabled so that multiple processors can request memory access. An eMMC controller is designed based on the proposed architecture using Verilog-HDL and is implemented using an FPGA.

Efficient implementation of computing unit for Hough transform

Advanced driver assistant system (ADAS) is widely adopted in smart cars and it is relied on image recognition algorithm. Hough transform is an essential algorithm for lane detection and traffic sign recognition in the ADAS and influences the detection ratio. The Hough transform is often implemented by hardware due to the heavy calculation. The Hough transform requires evaluation of sine and cosine functions. This paper proposes a computing scheme for the Hough transform. The proposed scheme enables continuous computing of sine and cosine values and designing efficient hardware architecture. The computing hardware for Hough transform is designed and compared with the previous works.

High performance on-chip-network architecture with multiple channels and dual routing

We design and implement an high performance on-chip-network, which is composed of Soc network architecture (SNA) and eXtended SoC Network Protocol (XSNP). The SNA is a hardware architecture for on-chip-buses, which provide simultaneous multiple channels and dual routing. The XSNP is an interface protocol for the SNA which provides compatibility with the AHB protocol. The SNA system is adequate for parallel processing systems with multiple processors. FIR filter systems are designed to verify the performance of the on-chip-bus using 1-, 2-layer AHB and the SNA. The performance is compared using simulation and implementing using FPGAs.