Chanseok Hwang

Sleep transistor distribution in row-based MTCMOS designs

The Multi-Threshold CMOS (MTCMOS) technology has become a popular technique for standby power reduction. This technology utilizes high-Vth sleep transistors to reduce sub threshold leakage currents during the standby mode of CMOS VLSI Circuits. The performance of MTCMOS circuits strongly depends on the size of the sleep transistors and the parasitics on the virtual ground network. Given a placed net list of a row-based MTCMOS design and the number of sleep transistor cells on each standard cell row, this paper introduces an optimal algorithm for linearly placing the allocated sleep transistors on each standard cell row so as to minimize the performance degradation of the MTCMOS circuit, which is in part due to unwanted voltage drops on its virtual ground network. Experimental results show that, compared to existing methods of placing the sleep transistors on cell rows, the proposed technique results in up to 11% reduction in the critical path delay of the circuit.

Statistical leakage estimation for DRAM circuits

Power consumption has become a key constraint in VLSI designs. Leakage current becomes a dominant part of the total power dissipation. In addition, with technology scaling into sub-50nm regime, one of the main design challenges in the presence of process variations is to cope with the uncertainties in timing and power. Since the leakage current is highly dominated by process variations, the statistical leakage estimation is essential for robust circuit design. Process variations can be monitored by analyzing the test element group (TEG). DRAM has power down mode with ICC2P parameter. To obtain ICC2P current, we need a long circuit-level simulation with an accurate transistor modeling. Therefore, to solve this problem, we need a practical framework which is based on switch-level and standby vector dependent statistical leakage analysis. In this paper, we proposed a TEG based analysis methodology to estimate the leakage current at ICC2P mode. Experiments on DRAM benchmark circuits demonstrate that the estimated results with our methodology are very accurate compared to the measurement data from industrial fabrication.

Analysis of electromagnetic field interference between an antenna and a multiple-noise source using active scattering parameters

This paper proposes an analysis method for electromagnetic field interference between an antenna and adjacent noise sources, using active scattering parameters. Electromagnetic field interference can be analyzed by measurement or simulation of the scattering parameters. In this paper, a multiple-band antenna and a multiple-noise source were designed and fabricated to analyze the electromagnetic field interference between them. The proposed analysis method employs active scattering parameters, whose validity has been verified both experimentally and through simulation.

Efficient circuit and EM model of electrostatic discharge generator

In this work, a new technique for an efficient, simple, and fast equivalent circuit and full wave numerical modeling of the electrostatic discharge (ESD) generator is presented. A novel circuit model of the NoiseKen ESD simulator is proposed based on the frequency domain measurement of the standard waveform calibration setup. The simple full wave electromagnetic model of the same generator, which requires much less computation resources, is also proposed using commercial CST Microwave Studio software. The reliability of the proposed models as an authentic ESD excitation source is validated through an example discharge application. The good agreement between the ESD reference waveform obtained through measurement, circuit model, and 3-D model of the generator is observed.

Effect of ESD generator ground strap configuration on ESD waveform

In this study, an analysis of the effect of the electrostatic discharge (ESD) gun grounding strap on the generated ESD stress waveform is presented. The reference ESD waveform is measured using the standard calibration setup of the IEC 61000-4-2 standard for the different (round, short and long) configurations of the grounding strap. The post processing analysis shows that increasing the length of the simulator ground strap to 3m reduces the variations in the ESD waveform, particularly ringing after the first peak, in comparison with standard reference waveform characteristics.

Fast power delivery network analyzer

With the increase in circuit frequency and supply voltage Scaling, a robust power network design is essential to ensure that the circuits on a chip operate reliably at the guaranteed level of performance. Traditionally the power network analysis has its main focus on IR-drop effects. However, IR drop analysis approaches have strong dependence on the input vectors and may require a tremendously long execution time. In this paper, we propose a novel and fast power network analysis method which calculates the effective resistance between all power pads and power grids. This method explores huge parasitic power networks and detects hot spots with an abnormal effective resistance value resulted from gross errors in the post-layout power network. We currently use the proposed method for our memory and DDI circuits to validate the post-layout power network quickly. We developed our method by using multi-thread and multi-process techniques, resulting in up to 50 times speed improvement.