Chaosong Gao

MAPS development for the ALICE ITS upgrade

Monolithic Active Pixel Sensors (MAPS) offer the possibility to build pixel detectors and tracking layers with high spatial resolution and low material budget in commercial CMOS processes. Significant progress has been made in the field of MAPS in recent years, and they are now considered for the upgrades of the LHC experiments. This contribution will focus on MAPS detectors developed for the ALICE Inner Tracking System (ITS) upgrade and manufactured in the TowerJazz 180 nm CMOS imaging sensor process on wafers with a high resistivity epitaxial layer. Several sensor chip prototypes have been developed and produced to optimise both charge collection and readout circuitry. The chips have been characterised using electrical measurements, radioactive sources and particle beams. The tests indicate that the sensors satisfy the ALICE requirements and first prototypes with the final size of 1.5 × 3 cm2 have been produced in the first half of 2014. This contribution summarises the characterisation measurements and presents first results from the full-scale chips.

A Low-Noise CMOS Pixel Direct Charge Sensor, Topmetal-II-

We report the design and characterization of a CMOS pixel direct charge sensor, Topmetal-II-, fabricated in a standard 0.35µm CMOS Integrated Circuit process. The sensor utilizes exposed metal patches on top of each pixel to directly collect charge. Each pixel contains a low-noise charge-sensitive preamplier to establish the analog signal and a discriminator with tunable threshold to generate hits. The analog signal from each pixel is accessible through time-shared multiplexing over the entire array. Hits are read out digitally through a column-based priority logic structure. Tests show that the sensor achieved a < 15 e analog noise and a 200 e = minimum threshold for digital readout per pixel. The sensor is capable of detecting both electrons and ions drifting in gas. These characteristics enable its use as the charge readout device in future Time Projection Chambers without gaseous gain mechanism, which has unique advantages in low background and low rate-density experiments.

Front end optimization for the monolithic active pixel sensor of the ALICE Inner Tracking System upgrade

ALICE plans to replace its Inner Tracking System during the second long shut down of the LHC in 2019 with a new 10 m2 tracker constructed entirely with monolithic active pixel sensors. The TowerJazz 180 nm CMOS imaging Sensor process has been selected to produce the sensor as it offers a deep pwell allowing full CMOS in-pixel circuitry and different starting materials. First full-scale prototypes have been fabricated and tested. Radiation tolerance has also been verified. In this paper the development of the charge sensitive front end and in particular its optimization for uniformity of charge threshold and time response will be presented.

A Low-Noise CMOS Pixel Direct Charge Sensor Topmetal-IIa for Low Background and Low Rate- Density Experiments

We present the design and characterization of a CMOS pixel direct charge sensor, Topmetal-IIa, fabricated in a standard 0.35µm CMOS process. The sensor features a 45 × 216 pixel array with a 40µm pixel pitch which collects and measures external charge directly through exposed metal electrodes in the topmost metal layer. Each pixel contains a low-noise charge-sensitive preamplifier to establish the analog signal, which is read out through time-shared multiplexing over the entire array. Compared to the earlier Topmetal-II- chip, the analog readout noise of Topmetal-IIa is reduced by 10.8% from 13.9e- to 12.4e-, and the DC voltage variation noise is reduced by 21% from 1.2mV down to 0.946mV. The sensor is capable of detecting both electrons and ions drifting in gas. These characteristics enable its use as the charge readout device in future Time Projection Chambers without gaseous gain mechanism, which has unique advantages in low background and low rate-density experiments.

Characterization of the column-based priority logic readout of Topmetal-II− CMOS pixel direct charge sensor

We present the detailed study of the digital readout of Topmetal-II- CMOS pixel direct charge sensor. Topmetal-II- is an integrated sensor with an array of 72X72 pixels each capable of directly collecting external charge through exposed metal electrodes in the topmost metal layer. In addition to the time-shared multiplexing readout of the analog output from Charge Sensitive Amplifiers in each pixel, hits are also generated through comparators with individually DAC settable thresholds in each pixel. The hits are read out via a column-based priority logic structure, retaining both hit location and time information. The in-array column-based priority logic is fully combinational hence there is no clock distributed in the pixel array. Sequential logic and clock are placed on the peripheral of the array. We studied the detailed working behavior and performance of this readout, and demonstrated its potential in imaging applications.

An asynchronous data-driven readout prototype for CEPC vertex detector

The Circular Electron Positron Collider (CEPC) is proposed as a Higgs boson and/or Z boson factory for high-precision measurements on the Higgs boson. The precision of secondary vertex impact parameter plays an important role in such measurements which typically rely on flavor-tagging. Thus silicon CMOS Pixel Sensors (CPS) are the most promising technology candidate for a CEPC vertex detector, which can most likely feature a high position resolution, a low power consumption and a fast readout simultaneously. For the R&D of the CEPC vertex detector, we have developed a prototype MIC4 in the Towerjazz 180 nm CMOS Image Sensor (CIS) process. We have proposed and implemented a new architecture of asynchronous zero-suppression data-driven readout inside the matrix combined with a binary front-end inside the pixel. The matrix contains 128 rows and 64 columns with a small pixel pitch of 25 μm. The readout architecture has implemented the traditional OR-gate chain inside a super pixel combined with a priority arb...

Topmetal-II−: a direct charge sensor for high energy physics and imaging applications

Topmetal-II−, a direct charge sensor, was manufactured in an XFAB 350 nm CMOS process. The Topmetal-II− sensor features a 72 × 72 pixel array with an 83 μm pixel pitch which collects and measures charge directly from the surrounding media. We introduce the implementation of the circuitry in the sensor including an analogue readout channel and a column based digital readout channel. The analogue readout channel allows the access to the full waveform from each pixel through a time-shared multiplexing. The digital readout channel records hits identified by an individually settable threshold in each pixel. Some simulation and preliminary test results are also discussed.

A CMOS 0.18 μm 600 MHz clock multiplier PLL and a pseudo-LVDS driver for the high speed data transmission for the ALICE Inner Tracking System front-end chip

This work presents the 600 MHz clock multiplier PLL and the pseudo-LVDS driver which are two essential components of the Data Transmission Unit (DTU), a fast serial link for the 1.2 Gb/s data transmission of the ALICE inner detector front-end chip (ALPIDE). The PLL multiplies the 40 MHz input clock in order to obtain the 600 MHz and the 200 MHz clock for a fast serializer which works in Double Data Rate mode. The outputs of the serializer feed the pseudo-LVDS driver inputs which transmits the data from the pixel chip to the patch panel with a limited number of signal lines. The driver drives a 5.3 m-6.5 m long differential transmission line by steering a maximum of 5 mA of current at the target speed. To overcome bandwidth limitations coming from the long cables the pre-emphasis can be applied to the output. Currents for the main and pre-emphasis driver can individually be adjusted using on-chip digital-to-analog converters. The circuits will be integrated in the pixel chip and are designed in the same 0.18 μm CMOS technology and will operate from the same 1.8 V supply. Design and test results of both circuits are presented.