Charayaphan Charoensak

Design of optimal and narrow-band Laguerre filters for sigma-delta demodulators

Conventional sigma-delta (/spl Sigma/-/spl Delta/) decimation methods are not optimal because the downsampling operation following the noise-shaping filters enables some quantization noise to alias back into the baseband. This paper proposes a novel decimation method that simplifies the implementation of the decimation process. This method makes use of an optimal Laguerre filter as the noise-shaping filter followed by another Laguerre filter that acts as a narrow-band filter. Conventional finite-impulse response (FIR) low-pass filters such as the optimal FIR filter and Sinc/sup k/ filter are commonly used as noise-shaping filters in /spl Sigma/-/spl Delta/ demodulators. As an alternative, optimal infinite-impulse response (IIR) filter architecture based on orthonormal Laguerre functions is used in the proposed decimation scheme. An optimal Laguerre IIR filter design methodology is presented via the optimization of a quadratic function subject to a linear and quadratic constraint. An efficient procedure to perform the optimization is introduced. A Laguerre IIR filter can also be used as the narrow-band filter before the decimation process. In this paper, a narrow-band Laguerre filter design methodology is presented via a digital frequency transformation. The narrow-band Laguerre filter can then be efficiently designed using a min-max criterion via a modified Parks-McClellan FIR filter design algorithm.

Performance evaluation of 3rd order sigma-delta (/spl Sigma/-/spl utri/) modulators via FPGA implementation

Sigma-delta (/spl Sigma/-/spl utri/) modulators have been widely used over the last few decades, in various signal processing applications. Usually, for improved signal-to-noise (quantization) performances, higher order modulators are utilized in these applications. In this paper, we investigate the performance of third order Sigma-delta (/spl Sigma/-/spl utri/) modulators and corresponding demodulators via Field Programmable Gate Array (FPGA) implementations. Two modulator architectures, the multi-stage (MASH) /spl Sigma/-/spl utri/ architecture and the Look Ahead Decision Feedback (LADF) /spl Sigma/-/spl utri/ architecture are compared on their performances. It is shown that the LADF /spl Sigma/-/spl utri/ architecture, which has not been widely reported in the literature, is preferable over the other modulators in the design of /spl Sigma/-/spl utri/ modulators. The selection of demodulator filters for reducing quantization noise resulting from the MASH and LADF /spl Sigma/-/spl utri/ architectures is also addressed in the paper. Advantages and disadvantages of various demodulator filters, e.g. sinc filters and recursive filters are discussed via the FPGA implementation.

Design of low-cost FPGA hardware for real-time ICA-based blind source separation algorithm

Blind source separation (BSS) of independent sources from their convolutive mixtures is a problem in many real-world multisensor applications. In this paper, we propose and implement an efficient FPGA hardware architecture for the realization of a real-time BSS. The architecture can be implemented using a low-cost FPGA (field programmable gate array). The architecture offers a good balance between hardware requirement (gate count and minimal clock speed) and separation performance. The FPGA design implements the modified Torkkolas BSS algorithm for audio signals based on ICA (independent component analysis) technique. Here, the separation is performed by implementing noncausal filters, instead of the typical causal filters, within the feedback network. This reduces the required length of the unmixing filters as well as provides better separation and faster convergence. Description of the hardware as well as discussion of some issues regarding the practical hardware realization are presented. Results of various FPGA simulations as well as real-time testing of the final hardware design in real environment are given.

A Framework for the Design and Implementation of a Dynamic Face Tracking System

This paper presents a 3-tier dynamic face tracking system (DFTS) framework based on Gabor wavelets. The proposed system is composed of three major modules: face detection unit, Gabor decomposition & similarity computation unit and face-lock refinement unit. First, we present a neural network based face detection that is used for face localization in cluttered environments. Subsequently, Gabor decomposition using a Gabor wavelet filter bank with 40 filters (8 orientations and 5 scales) of the initial image with the detected face, is carried out for facial feature point (FFP) extraction and initialization. In the next stage, similarity algorithms along with gabor wavelet decomposition are used to track the movements of FFPs in the faces. Finally, a face-lock mechanism using a subset of MPEG-4 facial definition parameters (FDP) is utilized to fine-tune the face tracking system under partial occlusion conditions. Most of the current face tracking systems need the FFPs to be labeled manually. They assume that the targeted face has already been detected and localized. In our proposed approach, face detection followed by automatic initialization of FFPs using Gabor wavelets is done to facilitate face tracking in a seamless manner. Rapid prototyping of FPGAs to speed up the compute- intensive tasks was performed.

Optimum sigma-delta (/spl Sigma/-/spl Delta/) de-modulator filter implementation via FPGA

Sigma-delta (/spl Sigma/-/spl Delta/) modulators have been widely used over the last few decades, in various signal processing applications. Usually, sigma-delta modulators produce single-bit outputs and thus are well suited for VLSI circuits which could be implemented using a small number of multipliers. For improved signal-to-noise (quantization) performances, higher order modulator schemes with multiloop and multi-stage architecture are utilized in most of the sigma-delta applications. The quantization noise behaviour of these higher order modulators is well known. Based on the quantization noise characteristics various de-modulator filter architectures, such as optimal FIR, Sinc filters and Laguerre HR filters are reported in the literature. In this paper, the VLSI implementation issues of these various demodulator filters are investigated. For this purpose the demodulators are implemented using Field Programmable Gate Array (FPGA) architecture.

FPGA design of a real-time implementation of dynamic range compression for improving television picture

This paper presents efficient FPGA hardware architecture for the implementation of a digital video processing algorithm for improving picture quality when displayed on devices such as LCD and PDP panels. The algorithm performs dynamic range compression on the photographic quality input video and produces the output suitable for displaying on the panel. The algorithm is based on bilateral filter. Bilateral filter is a type of non-iterative smoothing filter that preserves edge information. The proposed architecture demonstrates a good compromise between filter performance and FPGA resource requirements. The architecture was prototyped in hardware using FPGA. The design and simulation was carried out using system-level approach.

FPGA implementation of a sigma-delta (/spl Sigma/-/spl Delta/) architecture based digital I-F stage for software radio

A bandpass sigma-delta (/spl Sigma/-/spl Delta/) modulator architecture based digital I-F stage, suitable for software radio technology is investigated. The I-F stage separates the in-phase and quadrature (I and Q) signals using a single circuit path, thus eliminating any I-Q differences due to component mismatch. The separated I-Q signals can then be used in a subsequent DSP stage such as software FM demodulator that is compatible with digital wireless or FM receiver systems. The performance of the single path circuit in terms of quantization noise and I-Q signal mismatch effects is analyzed in detail. Based on this analysis, criteria for the selection of designing parameters, such as sampling frequency and oversampling ratio are presented. Issues related to hardware realization of the I-F stage using a field programmable gate array (FPGA) are discussed and a system level approach to the design of the FPGA is shown. Although FPGA does not offer optimized hardware implementation when compared to ASIC (application specific integrated circuit), it allows short design time and enables rapid verification of algorithms in hardware.

Efficient Realization of Sigma-Delta ( - ) Kalman Lowpass Filter in Hardware Using FPGA

Sigma-delta (Open image in new window-Open image in new window) modulation techniques have moved into mainstream applications in signal processing and have found many practical uses in areas such as high-resolution A/D, D/A conversions, voice communication, and software radio.Open image in new window-Open image in new window modulators produce a single, or few bits output resulting in hardware saving and thus making them suitable for implementation in very large scale integration (VLSI) circuits. To reduce quantization noise produced, higher-order modulators such as multiloop and multistage architectures are commonly used. The quantization noise behavior of higher-orderOpen image in new window-Open image in new window modulators is well understood. Based on these quantization noise characteristics, various demodulator architectures, such as filter, optimal FIR filter, and Laguerre filter are reported in literature. In this paper, theory and design of an efficient Kalman recursive demodulator filter is shown. Hardware implementation of Kalman lowpass filter, using field programmable gate array (FPGA), is explained. The FPGA synthesis results from Kalman filter design are compared with previous designs for sinc filter, optimum FIR filter, and Laguerre filter.Sigma-delta (-) modulation techniques have moved into mainstream applications in signal processing and have found many practical uses in areas such as high-resolution A/D, D/A conversions, voice communication, and software radio.- modulators produce a single, or few bits output resulting in hardware saving and thus making them suitable for implementation in very large scale integration (VLSI) circuits. To reduce quantization noise produced, higher-order modulators such as multiloop and multistage architectures are commonly used. The quantization noise behavior of higher-order- modulators is well understood. Based on these quantization noise characteristics, various demodulator architectures, such as filter, optimal FIR filter, and Laguerre filter are reported in literature. In this paper, theory and design of an efficient Kalman recursive demodulator filter is shown. Hardware implementation of Kalman lowpass filter, using field programmable gate array (FPGA), is explained. The FPGA synthesis results from Kalman filter design are compared with previous designs for sinc filter, optimum FIR filter, and Laguerre filter.

Performance evaluation of a third-order LADF sigma-delta (Σ-Δ) modulator via FPGA implementation

Over the last few decades, sigma-delta (Σ-Δ) modulators have been widely used in various signal processing applications. In these applications, for improved signal-to-noise ratio performances, higher order modulators are used. In this paper, we investigate the performance of a third-order Look Ahead Decision Feedback (LADF) ΣΔ A modulator. It is shown that the LADF ΣΔ modulator, which has not been widely reported in the literature, is efficient and offers attractive features for hardware implementation. These features are investigated via the use of a system level design for Field Programmable Gate Array prototyping of the LADF modulator.

FaceProcessor: A Framework for Hardware Design and Implementation of a Dynamic Face Tracking System

This paper presents a 3-tier framework for hardware implementation of dynamic face tracking system (DFTS) based on Gabor wavelets. The proposed system is composed of three major modules: Face detection unit, Gabor decomposition & Similarity computation unit and Face-lock refinement unit. First, we present a neural network based face detection that is used for face localization in cluttered environments. Subsequently, Gabor decomposition using a Gabor wavelet filter bank with 40 filters (8 orientations and 5 scales) of the initial image with the detected face, is carried out for facial feature point (FFP) extraction and initialization. In the next stage, similarity algorithms along with Gabor wavelet decomposition are used to track the movements of FFPs in the faces. Finally, a face-lock mechanism using a subset of MPEG-4 facial definition parameters (FDP) is utilized to fine-tune the face tracking system under partial occlusion conditions. Most of the current face tracking systems need the FFPs to be labeled manually. They assume that the targeted face has already been detected and localized. In our approach, face detection followed by automatic initialization of FFPs uses Gabor wavelets to facilitate face tracking in a seamless manner. Rapid prototyping of FPGAs speeds up the compute-intensive tasks