Charles Anthony Odegard

Dielectric Integrity Test for Flip-Chip Devices with Cu/Low-k Interconnects

Migration to low-k dielectric materials in wafer-fab backend-of-line (BEOL) interconnect schemes is necessary for improved electrical performance of smaller and tighter geometries enabled by advanced silicon technology nodes. Unfortunately, low-k dielectrics are mechanically weaker compared to previous generation materials. Concurrent technology and market driven changes such as tighter bump pitch and replacing SnPb with Pb-free solder bump composition are leading to increased stress and risk to damage of the inherently weaker dielectrics in flip-chip packages. It is, hence, critical to characterize the structural integrity of the BEOL interconnect schemes containing low-k dielectrics. Traditional environmental reliability stress testing, while effective, is time-consuming and expensive, and not conducive for fast learning cycles required during early development phases. This paper demonstrates the utility of a test that enables rapid and accurate assessment of the mechanical integrity of low-K dielectrics. Silicon dies with Cu/low-k interconnect are assembled on to an organic substrate through flip-chip bumps, and cooled. The mismatch in coefficient of thermal expansion (CTE) between the silicon die and organic substrate can induce failure if the resulting thermal residual stress exceeds the strength of the structure. Since the level of thermal residual stress depends on the temperature, the magnitude of induced stress can be controlled by subjecting the sample to various degrees of cooling. Consequently, the strength of the BEOL structures can be determined, in conjunction with thermo-mechanical stress analyses results from finite element simulation of the test.

Effect of compatibility between fluxes and cyanate ester underfill on lead free flip chip assembly and reliability

The quality and reliability of flip-chip assembly is severely impacted by the compatibility between various materials used in the package. Currently, no-clean fluxes are widely used for the assembly of flip chips. Poor compatibility between the flux residue and the underfill can lead to the formation of voids, and consequently, reliability problems. Therefore, a major concern for flip-chip assembly is the compatibility between the flux residues and the underfill. The principal objective of this research was to develop a flux for lead-free packaging, which would be compatible with high performance moisture resistant cyanate ester-based underfills. During this study, commercially available fluxes, along with tailor made epoxy-based flux, were tested for their compatibility with the underfill. The results indicated that the assembly process window for the rosin-based fluxes was much wider than the epoxy-based fluxes. Synthetic flux had poor soldering performance and relatively poor compatibility with the cya...

Dielectric integrity test for flip-chip devices with Cu/low-k interconnects

Migration to low-k dielectric materials in wafer-fab back-end-of-line (BEOL) interconnect schemes is necessary for improved electrical performance of smaller and tighter geometries enabled by advanced silicon technology nodes. Unfortunately, low-k dielectrics are mechanically weaker compared to previous generation materials. Concurrent technology and market driven changes such as tighter bump pitch and replacing SnPb with Pb-free solder bump composition are leading to increased stress and risk to damage of the inherently weaker dielectrics in flip-chip packages. It is, hence, critical to characterize the structural integrity of the BEOL interconnect schemes containing low-k dielectrics. Traditional environmental reliability stress testing, while effective, is time-consuming and expensive, and not conducive for fast learning cycles required during early development phases. This paper demonstrates the utility of a test that enables rapid and accurate assessment of the mechanical integrity of low-k dielectrics. Silicon dies with Cu/low-k interconnect are assembled on to an organic substrate through flip-chip bumps, and cooled. The mismatch in coefficient of thermal expansion (CTE) between the silicon die and organic substrate can induce failure if the resulting thermal residual stress exceeds the strength of the structure. Since the level of thermal residual stress depends on the temperature, the magnitude of induced stress can be controlled by subjecting the sample to various degrees of cooling. Consequently, the strength of the BEOL structures can be determined, in conjunction with thermo-mechanical stress analyses results from finite element simulation of the test.