Charles C. Chiang

Wirability of knock-knee layouts with 45 degrees wires

The problem of wiring an arbitrary knock-knee layout (in a square grid with an arbitrary number of modules) in three and two layers using a small number of vias is investigated. A technique is proposed for transforming a knock-knee layout into a three-layer wirable layout by replacing knock-knees with 45 degrees wires. A 45 degrees replacing algorithm to achieve three-layer wirability is introduced. An efficient stretching technique to ensure two-layer wirability using 45 degrees wires is described. Conversion of an abstract layout into a corresponding physical layout is discussed. Experimental results are presented. >

Global routing based on Steiner min-max trees

Global routing of multiterminal nets is studied. A novel global router is proposed; each step consists of finding a tree, called a Steiner min-max tree, that is Steiner tree with maximum-weight edge minimized (real vertices represent channels containing terminals of a net, Steiner vertices represent intermediate channels, and weights correspond to densities). An O (min(e loglog e, n/sup 2/)) time algorithm is proposed for obtaining a Steiner min-max tree in a weighted graph with e edges and n vertices. (This result should be contrasted with the NP-completeness of the traditional minimum-length Steiner tree problem). Experimental results on difficult examples, on randomly generated data, on master slice chips, and on benchmark examples from the Physical Design Workshop are included. >

SAPOR: second-order Arnoldi method for passive order reduction of RCS circuits

The recently-introduced susceptance element exhibits many prominent features in modeling the on-chip magnetic couplings. For an RCS circuit, it is better to be formulated as a second-order system. Therefore, corresponding MOR (model-order reduction) techniques for second-order systems are desired to efficiently deal with the ever-increasing circuit scale and to preserve essential model properties. We first review the existing MOR methods for RCS circuits, such as ENOR and SMOR, and discuss several key issues related to numerical stability and accuracy of the methods. Then, a technique, SAPOR (second-order Arnoldi method for passive order reduction), is proposed to effectively address these issues. Based on an implementation of a generalized second-order Arnoldi method, SAPOR is numerically stable and efficient. Meanwhile, the reduced-order system also guarantees passivity.

A powerful global router: based on Steiner min-max trees

A study is made of the global routing of multiterminal nets. The authors propose a novel global router. Each step consists of finding a tree, called Steiner min-max tree, that is, a Steiner tree with the maximum-weight edge minimized (real vertices represent channels containing terminals of a net, Steiner vertices represent intermediate channels, and weights correspond to densities). An efficient algorithm is presented for obtaining a Steiner min-max tree, in a weighted graph. Experimental results on difficult examples, randomly generated data, master slice chips, and benchmark examples from the physical design workshop are very promising. (In all cases, previous results have been improved.).<<ETX>>

Efficient process-hotspot detection using range pattern matching

In current manufacturing processes, certain layout configurations are likely to have reduced yield and/or reliability due to increased susceptibility to stress effects or poor tolerance to certain processes like lithography. These problematic layout configurations need to be efficiently detected and eliminated from a design layout to enable better yield. In this paper, such layout configurations are called process-hotspots and an efficient and scalable algorithm is proposed to detect such process-hotspots in a given layout. The concept of a range pattern is introduced and used to accurately and compactly represent these process-hotspots. This representation is flexible and can incorporate information about the deficiencies of available modeling and/or subsequent correction (for instance, mask synthesis) techniques. Each range pattern can also be associated with a scoring mechanism to score the problem regions according to yield impact. A library of range patterns is being developed in collaboration with a fab. The proposed process-hotspot detection system assumes that process-hotspots are specified as a library of range patterns and determines all occurrences of any of these range patterns in a layout. It is fast and accurate and can be applied to large industrial layouts. Unlike previous work, the proposed scheme can identify problems that cannot be efficiently modeled or corrected by subsequent mask synthesis techniques and can thereby complement existing work in that area. Experimental results are quite promising and show that all locations that match a range pattern in a given layout can be found in a matter of minutes

Accurate process-hotspot detection using critical design rule extraction

In advanced fabrication technology, the sub-wavelength lithography gap causes unwanted layout distortions. Even if a layout passes design rule checking (DRC), it still might contain process hotspots, which are sensitive to the lithographic process. Hence, process-hotspot detection has become a crucial issue. In this paper, we propose an accurate process-hotspot detection framework. Unlike existing DRC-based works, we extract only critical design rules to express the topological features of hotspot patterns. We adopt a two-stage filtering process to locate all hotspots accurately and efficiently. Compared with state-of-the-art DRC-based works, our results show that our approach can reach 100% success rate with significant speedups.

The road to 3D EDA tool readiness

Todays SoCs/SIPs face numerous design challenges as increased integration of system components on a single die stretches the limits of technology and design capacity. 3D integration, where multiple dies are stacked and interconnected in the vertical dimension using through-silicon vias (TSVs), is probably the best hope for carrying ICs along (and even beyond) the path of Moores law in the 21st century. However successful adoption of 3D ICs will require among other things modifications to EDA tools to enable 3D IC design. In this paper, we identify key stages in EDA that need modification to handle 3D ICs, highlight the challenges and review existing solutions, if they exist. Whenever appropriate, at a particular stage, we also provide preferred features of the solutions necessary to enable 3D IC design with the least amount of disruption.

A layout dependent full-chip copper electroplating topography model

In this paper, a layout dependent full-chip electroplating (ECP) topography model is developed based on the additive nature of the physics of the EP process. Two layout attributes: layout density, and feature perimeter sum are used to compute the post-ECP topography. Under a unified mechanism, two output variables representing the final topography: the array height and the step height are modeled simultaneously. Using the proposed model long-range effects of the ECP process can be incorporated easily as well. The simulation results of our model were verified with test structure experimental data published in the literature and are presented in this paper. The results show that the errors are less than 5%. This model is not limited to the regular test structures; it can also be used for any practical design. The results of such partial application are shown here as well. Our proposed ECP model can be used to model systematic variations caused by an ECP process or by a chemical mechanical planarization (CMP) process. The potential applications of this model include: layout design evaluation for catastrophic failure prevention; yield aware design (design for manufacturability), and variation- aware timing analysis.

Accurate detection for process-hotspots with vias and incomplete specification

This paper introduces the concept of via range patterns and incompletely specified range patterns to represent new types of process-hotspots. Via range patterns can represent process-hotspots containing vias that are a major source of lithography issues. An incompletely specified range pattern can accurately and succinctly represent a process-hotspot where any configuration of objects (that is unknown to the user apriori) can exist in some of its peripheral regions. These new types of range patterns cannot be accurately represented and/or detected using the concept of range patterns introduced in [7]. A new detection algorithm that can accurately detect these new types of patterns is also proposed. This is necessitated since the range pattern matching algorithm proposed earlier causes mismatches: it either misses true matches or reports false matches for these new kinds of patterns. Theoretical results show that the proposed algorithm prevents the incorrect mis-match issues, while experimental results on fab provided process-hotspots show the algorithm is computationally efficient and practical for use on real industrial designs.

Accurate modeling of substrate resistive coupling for floating substrates

This article focuses on the formulation of the substrate resistive coupling using boundary element methods, specifically for substrates without grounded backplates (floating substrates). An accurate and numerically stable formulation is presented. Numerical results are shown to demonstrate the correctness and the numerical robustness of the formulation.