Charles D. Lane

A 100-dB SFDR 80-MSPS 14-Bit 0.35-

This paper describes a 14-bit 80-MSPS ADC with 100-dB SFDR at 70-MHz input frequency in a 0.35-mum single-well BiCMOS technology drawing 1.2 W from a dual 3.3 V/5.0 V supply. Key barriers to high dynamic range in pipeline ADCs at high clock rates and some methods to overcome these barriers will be presented. These methods include a sampling front-end without the use of a designated Sample and Hold (S/H). A BiCMOS switching input buffer is used along with the strategic use of BiCMOS design techniques. Also, calibration is combined with capacitor shuffling to maximize linearity with minimal noise impact

muhbox m

The cellular infrastructure market requires high clock rate, high dynamic range ADCs to enable efficient, advanced architecture receive channels. This paper describes a 14 bit 80MSPS ADC with 100dB+ SFDR at baseband in 0.35/spl mu/m BiCMOS technology using 1.1 watts on a 3.3V/5.0V dual supply. Some challenges associated with high spurious free dynamic range at high clock rates will be discussed along with methods used in this ADC to overcome these barriers.