Charles E. Moore

A Versatile 90-nm CMOS Charge-Pump PLL for SerDes Transmitter Clocking

This paper presents a low-jitter charge-pump phase-locked loop (PLL) built in standard 90-nm CMOS for 1 to 10 Gb/s wireline SerDes transmitter clocking. The PLL employs a programmable dual-path loop filter with integral path and resistorless sample-reset proportional path that are independently controlled for flexible setting of closed-loop bandwidth and peaking. Frequency is synthesized by a digitally calibrated LC-VCO achieving 45% calibration tuning range with inversion-mode nMOS varactors and area-efficient helical inductors. Following calibration, 4.8% hold range compensates for VCO sensitivity to supply voltage and temperature drift. The PLL exhibits 0.81 ps rms jitter at 10 Gb/s. Critical for ASICs integrating noisy digital cores and multiple SerDes channels, design considerations to minimize jitter induced by supply noise are described. Deep-submicron CMOS effects on design are also examined to improve manufacturability and performance

A versatile low-jitter PLL in 90-nm CMOS for SerDes transmitter clocking

A low-jitter charge-pump PLL is built in 90-nm CMOS for 1-10 Gb/s SerDes transmitter clocking. The PLL employs a programmable dual-path loop filter with integrating path and novel resistorless proportional path that can be independently controlled and accurately modeled for flexible setting of closed-loop bandwidth and peaking. Frequency is synthesized using an area-efficient LC-VCO with helical inductors and inversion-mode nFET varactors for 45% tuning range. The PLL exhibits 0.81 ps rms jitter at 10.0 Gb/s. Technology considerations for improving design manufacturability, tuning range, and jitter performance are addressed.

A CMOS analog adaptive equalizer for a DDSS tape drive PRML read channel

A fully analog approach to an adaptive equalizer is designed in 1.0 /spl mu/m CMOS. The 13 tap FIR filter is a key component of a PRML read/write channel mixed signal IC for digital audio tape (DAT) format tape drives. A variety of continuous time, current mode, switched capacitor, and offset cancellation techniques are used to achieve desired performance.