Charles J. Camp

Using adaptive read voltage thresholds to enhance the reliability of MLC NAND flash memory systems

NAND Flash memory is not only the ubiquitous storage medium in consumer applications, but has also started to appear in enterprise storage systems as well. MLC and TLC Flash technology made it possible to store multiple bits in the same silicon area as SLC, thus reducing the cost per amount of data stored. However, at current sub-20nm technology nodes, MLC Flash devices fail to provide the levels of raw reliability, mainly cycling endurance, that are required by typical enterprise applications. Advanced signal-processing and coding schemes are needed to improve the Flash bit error rate and thus elevate the device reliability to the desired level. In this paper, we report on the use of adaptive voltage thresholds in the read operation of NAND Flash devices. We discuss how the optimal read voltage thresholds can be determined, and assess the benefit of adapting the read voltage thresholds in terms of cycling endurance, data retention and resilience to read disturb.

Enhancing the Reliability of MLC NAND Flash Memory Systems by Read Channel Optimization

NAND flash memory is not only the ubiquitous storage medium in consumer applications but has also started to appear in enterprise storage systems as well. MLC and TLC flash technology made it possible to store multiple bits in the same silicon area as SLC, thus reducing the cost per amount of data stored. However, at current sub-20nm technology nodes, MLC flash devices fail to provide the levels of raw reliability, mainly cycling endurance, that are required by typical enterprise applications. Advanced signal processing and coding schemes are needed to improve the flash bit error rate and thus elevate the device reliability to the desired level. In this article, we report on the use of adaptive voltage thresholds and cell-to-cell interference cancellation in the read operation of NAND flash devices. We discuss how the optimal read voltage thresholds can be determined and assess the benefit of cancelling cell-to-cell interference in terms of cycling endurance, data retention, and resilience to read disturb.

Effect of Read Disturb on Incomplete Blocks in MLC NAND Flash Arrays

The effect of read disturb on partially programmed blocks of MLC NAND is evaluated using experimental data from 2y-, 1y- and 1x-nm Flash memory devices. We demonstrate that when a partially programmed block is exposed to a large number of reads before it is finalized in terms of page programming, the remaining pages will exhibit a significant bit error-rate (BER) increase. The page-BER is characterized in terms of program-erase cycles and read cycles and is further analyzed based on the programmed threshold voltage distributions. The impact of the page programming algorithm is also discussed.