Charles Thangaraj

Characterization of CMOS compatible waveguide-coupled leaky-mode photodetectors

Near-field scanning optical microscopy has been employed for the first time to analyze integrated photodetectors. Waveguide-coupled leaky-mode polysilicon metal-semiconductor-metal photodiodes fabricated in commercial complementary metal-oxide-semiconductor technology for on-chip optical interconnects exhibit a measured effective absorption coefficient of 0.67 dB/mum allowing a 10-mum-long detector to absorb 83% of the light in the waveguide with an estimated responsivity of 0.35 A/W at 654 nm. The measured effective absorption coefficient is in good agreement with effective index mode overlap calculations

Fully CMOS-Compatible On-Chip Optical Clock Distribution and Recovery

Clock distribution in the multi-gigahertz range is getting increasingly difficult due to more stringent requirements for skew and jitter on one hand and the deteriorating supply voltage integrity and process variation on the other hand. Global clock network, especially in nanometer CMOS designs with ever increasing die sizes, has become a prominent performance limiter. A potential alternative to traditional interconnect technology for achieving clock distribution beyond 10 GHz while maintaining required skew and jitter budgets is using on-chip optical interconnects. A practical on-chip optical clocking system must be CMOS compatible in order to provide attractive cost effectiveness for system level integration and ease of manufacturing. This paper presents the design of a fully CMOS compatible optical clock distribution and recovery system in a 3.3 V, 0.35-μm CMOS process. Experimental results from the test chip prove the feasibility of providing optical-electrical interface in devices and circuits in a fully CMOS compatible manufacturing environment. Although the test chips were designed in a mature CMOS process technology and the measured performance is low, the test chips demonstrated the feasibility of on-chip optoelectronic integration with fully CMOS compatible process. On-chip optical clock distribution is one of the natural applications of fully CMOS compatible on-chip optical interconnect technology.

Waveguide coupled CMOS photodetector for on-chip optical interconnects

A novel, truly CMOS compatible, waveguide coupled, high-speed photodiode for on-chip optical clock distribution is designed using analytical calculations, electro-optical simulations, and experimental analysis. Experiment and simulation results from test devices are presented and analyzed. Results from test devices and waveguides currently under fabrication in the Agilent 0.35 /spl mu/m CMOS process will be reported.

Rapid design space exploration using legacy design data and technology scaling trend

Rapid and effective design space exploration at all stages of a design process enables faster design convergence and shorter time-to-market. This is particularly important during the early stage of a design where design decisions can have a significant impact on design convergence. This paper describes a methodology for design space exploration using design target prediction models. These models are driven by legacy design data, technology scaling trends and, an in situ model-fitting process. Experiments on ISCAS benchmark circuits validate the feasibility of the proposed approach and yielded power centric designs that improved power by 7-32% for a corresponding 0-9% performance impact; or performance centric designs with improved performance of 10.31-17% for a corresponding 2-3.85% power penalty. Evolutionary algorithm based Pareto analysis on an industrial 65nm design uncovered design tradeoffs which are not obvious to designers and optimize both power and performance. The high performance design option of the industrial design improved the straight-ported designs performance by 29% with a 2.5% power penalty, whereas the low power design option reduced the straight-ported designs power consumption by 40% for a 9% performance penalty.

Power andPerformance Analysis for Early Design Space Exploration

Early design space exploration is crucial to achieving optimal designs, when it is increasingly difficult to fit a design into a tight design space. System level exploration needs to be coupled with physical design considerations to guarantee design closure and time-to-market. This paper presents a methodology for early design space exploration aimed at power-delay trade-offs. The proposed methodology allows quick what-if analysis incorporating many design techniques. What-if analysis is performed on three ISCAS85 benchmark circuits to ascertain recipes for power or performance centric designs. Using the proposed methodology we demonstrate 32%, 17% and 32% reduction in power for 9%, 4.3% and 1.3% performance penalty respectively, the what-if analysis also shows 11.25%, 10.31% and 15.3% improvement in performance for 2.35%, 2.43% and 3.85% increase in power, respectively if the same circuits were made performance centric.

Design of clock recovery circuits for optical clocking in DSM CMOS

CMOS technology scaling especially in the sub-100 nm regime has made signaling in long global a challenge, resulting in a need for an improved interconnect technology. Optical signalling is a promising alternative to existing global interconnects and alleviates interconnect bottle-neck. This paper presents a design of a CMOS trans-impedance amplifier (TIA) that is intended for a truly CMOS compatible on-chip optical clock distribution system. This TIA employs replica biasing technique to achieve stability while maximizing its bandwidth and gain. The design was implemented in a 0.35μm CMOS process and is currently under probe testing. The simulation results show that the design achieved a bandwidth of 1GHz and gain of 128dB-Ω. Extensive Monte-Carlo simulations indicate the superior characteristics of stability under a variety of process and environmental variations.

DC and AC performance of leaky-mode metal-semiconductor-metal polysilicon photodetectors

Metal-semiconductor-metal (MSM) polysilicon photodetectors which are compatible with all standard complementary metal-oxide-semiconductor (CMOS) processes and which were made in a commercial 0.35 ìm process have demonstrated DC responsivities up to 1.3 A/W at 690 nm. An effective absorption coefficient of 0.63 dB/ìm was found from a comparison of responsivities of 5- and 10-μm long detectors. For a constant bias voltage, responsivity varies as the inverse square of the contact spacing, with responsivity continuing to increase for the smallest available contact spacing devices. Responsivities corresponding to quantum efficiencies over 200% were observed, implying a gain mechanism. For AC performance, electrical pulse full-width at half-maximum (FWHM) as low as 0.81 ns and 10% - 90% rise times as low as 0.39 ns have been measured in response to ~0.65 ns FWHM optical input pulses. The ability to modulate the source laser diode limits the measured pulse performance of the detectors. Observed DC and pulse results are well explained by an analytic expression which incorporates the effects of bulk and contact recombination. Possible means of improving the detector speed are proposed.2

Early Design Phase Power Performance Trade-Offs Using In-Situ Macro Models

Early phase space exploration with a focus on power performance tradeoffs has been shown to enable faster design convergence. Tightly coupled physical design considerations and system level models are needed to guarantee time-to- market. This paper describes a methodology for early design space exploration. A Pareto-front analysis using the proposed methodology was applied to an industrial design to perform design space exploration. The obtained low power design solution improved the designers best solution by additionally reducing power by 6% with 2% performance impact. The optimal trade-off solution improved designers best by additionally trading off 1.7% and 2.8% performance for power savings of 8.5% and 7.6% respectively. The absolute amount achieved here is not as important as knowing what the desired design options should be for each functional block in the design very early in the design phase.

Design target exploration for meeting time-to-market using pareto analysis

Early design phase space exploration, power validation and performance estimation will enable faster design convergence and shorter time-to-market. System level models based on physical design parameters, in-situ macro models and background SPICE simulation improves overall model accuracy. This paper describes a pareto analysis methodology for design target generation to meet time-to-market constraint; illustrating design choice generation algorithm and a test circuit SPICE validation. Power and performance centric design solutions (targets) that are not obvious to the designers are explored. Pareto analysis yielded power centric design target that improved both system power consumption and performance by 19.6% and 6.3% respectively. Performance centric design target improved system level performance and power by 11.7% and 1.63% respectively.

Optical characterization of a leaky-mode polysilicon photodetector using near-field scaning optical microscopy

Near-field scanning optical microscopy was used to characterize the light absorption capability of a leaky-mode coupled polysilicon photodetector fabricated for CMOS on-chip optical interconnects. The observed results are in good agreement with modal calculations.