Charles Trullemans

From KCL to Class D Amplifier

From a circuit point of view, the starting point of the students coming out of the secondary school is roughly limited to describing the flow of electrical charges through a simple loop. Nevertheless, one and a half years later, they can design, simulate, build and test the core of a Class D amplifier while meeting demanding learning objectives. This paper relates the story of a project conducted in the context of an undergraduate electrical engineering program. Circuits and system concepts are introduced from the beginning of the first year in a physics course, and are applied to a project during the second term. A circuit theory course and the Class D amplifier project are run in parallel during the second term of the second year. Effective learning is facilitated by a mixture of lectures covering the necessary concepts and self- directed laboratory experiments allowing active acquisition of problem solving skills. At the end of the project, enthusiastic students can listen to the sound of their MP3 player through the amplifier that results from their teamwork. A survey indicates that the outcomes of the project are in line with the expected results of a problem- and project-based learning environment.

Logic Verification of Incomplete Functions and Design Error Location

At the stage of logic verification, it is necessary not only to detect but also to locate the sources of design errors that may exist in the gate-level circuit. For an incompletely specified function, a method to compute the corresponding 3-terminal BDD that represents the ON-set, OFF-set and DC-set, is described. Two incomplete functions are equivalent if, and only if, their 3-terminal BDDs are isomorphic. If the gate-level circuit is verified to be incorrect, a conditional stuck-at fault model is proposed to represent the circuit with design errors. The incorrect logic values at the design error sites can be considered as conditional stuck-at faults. A design error locating method, based on fault simulation and released pattern generation, is described.

Improving BDDs manipulation through incremental reduction and enhanced heuristics

The authors present techniques leading to small binary decision diagrams (BDDs) for combinational functions. They propose some new heuristics for computing an initial variable ordering, one of which is shown to represent a significant enhancement over the best ones the authors could find in the literature. Additionally, they introduce a novel incremental method, devised to quickly change the variable ordering intrinsic to these diagrams. They discuss an application of this method involving the reduction of the size of diagrams after their construction. Comparison with previously published results is provided.<<ETX>>

Compaction of CD(2 k -D) control unit architectures

Abstract A topological hardware solution to compact CD(2k−D) control unit architectures [2] without decreasing their speed is presented in this paper. In addition, a cost analysis in terms of ROM size is carried out to select the most appropriate architecture for a given algorithm to be implemented. Also discussed is a logical optimization phase based on the new hardware solution and on the logical PLA optimization theory. The CD(2k−D) control unit compaction is automatically generated by a control unit compiler [5].

A New Carry Free Division Algorithm and Application to a Single Chip 1024 bits RSA Processor

A new carry-free division algorithm will be described; it is based on the properties of RSD arithmetic to avoid carry propagation. Its application to a 1024 bits RSA cryptographic chip will also be presented. Thanks to the features of this new algorithm, high performance (8 kbits/s for 1024 bits words) was obtained for relatively small area and power consumption (80 mm2 in a 2 ¿m CMOS process and 500 mW at 25 MHz).

Brisc - a Risc Biprocessor Architecture Dedicated To Power Applications

Abstract This paper describes a new RISC processor whose architecture and programming suit well with typical algorithms developed in the expanding field of digital control of power devices. As a result, general-purpose or DSP-oriented processors can profitably be replaced by this new ASIC that integrates a double floating point datapath and ancillary circuits.

A switch level symbolic simulator

The simulator presented in this paper is based on a switch level model and is used to extract the logical behaviour of MOS digital integrated circuits. Its main original features are that the simulation is achieved symbolically with all its generality.

La compilation de silicium: une aide au développement de systèmes VLSI, orientée vers le domaine d'application

AnalyseLa compilation de silicium est une méthode de mise en place rapide et efficace d’algorithmes sur silicium. Les données fournies au compilateur sont une spécification abstraite du circuit, dans le langage du domaine d’application. La sortie est un dessin des masques. La compétence de l’utilisateur est attendue dans son propre domaine, et non dans le domaine de la conception de circuits sur silicium. Cependant, cette démarche n’est possible que dans des cas précis, dont le traitement de signal. De ce fait, les télécommunications en sont un champ d’application. La synthèse est faite dans un espace de solutions restreint, choisi d’après les propriétés désirées à chaque niveau: sensibilité, économie de surface, etc. La compilation de silicium est aujourd’hui essentiellement un domaine de recherches. Les programmes s’intéressent à la réalisation de structures spécialisées: chemin de données, traitement de signal, etc. Elle donne néanmoins déjà lieu à des réalisations industrielles.AbstractThe aim of silicon compilation is to provide a fast and effective way of implementing an algorithm on silicon. The input to a silicon compiler is an abstract specification of the wanted circuit, at a level close to the application level. The output is a layout of the chip. The skillness required from the user is the knowledge of the application domain, not an experience in designing integrated circuits. This process is however possible for well defined cases only. Signal processing is one of these cases, and therefore, this technique is well suited for the telecommunication area. The synthesis is performed in a reduced solution space, restricted to a class of solutions exhibiting good properties at each level: sensitivity, layout compactness, etc. Silicon compilation is mostly a research area today. Programmes are developed to deal with special structures as data paths, signal processors, etc. Nevertheless, this method has been successfully applied to the design of industrial products.