Charles W. Stirk

Sorting with optical compare-and-exchange modules

Sorting is central to the solution of many knowledge-based and switching problems in advanced computation and communication systems. Parallel-pipelined sorting algorithms are appropriate for applications that demand high throughput, low delay, and many data channels. One such algorithm, the bitonic sort, can be implemented with passive perfect shuffle interconnects between active stages of compare-and-exchange (C&E) elements. In this paper we focus on optical hardware to implement the C&E operation and show that, by taking advantage of a distinctive feature of optical logic, namely, bistability, comparison circuits of remarkable simplicity are attainable. We describe implementations of C&E in a variety of optical device technologies capable of performing latching and nonlatching logic. Based on the device characteristics we outline potential application areas for each technology.

Compact architectures for adaptive neural nets

A compact optical architecture capable of implementing a number of adaptive neural net models is described. Compact architectures do not involve traditional optical imaging systems and are potentially rugged, easily constructed, and scalable. The critical devices of the generic architecture include 1-D electro optic modulators and detectors to implement the neural processing elements, along with the Pockels readout optical modulator (PROM) to encode the analog weights. The architectural advancements include an input/output compatible method of handling both positive and negative values for the elements of the neuron activation vectors and the synaptic weight matrices during learning and recall. These hybrid architectures are capable of implementing linear and nonlinear associators with adaptive learning algorithms.

Bit error rate of optical logic: fan-in, threshold, and contrast

Bit error rates are calculated in the presence of shot noise for threshold optical logic devices that employ direct detection and intensity modulation. The device parameters considered are fan-in, contrast ratio, and light output. With given values for these parameters, the paper derives expressions for the device thresholds that generate the optimal bit error rates. In addition, it examines the fundamental quantum limit on reliability. Finally, the paper finds a bound on the device reliability that is sufficient to guarantee correct system operation with high probability.

Cost models of components for free-space optically interconnected systems

The cost of components for optically interconnected systems, such as optoelectronic device arrays and computer generated holograms, depends on their method of manufacture. In this paper, we built analytic models that measure component cost based on the cost and yield of each manufacturing step. Using these models we show that for large optoelectronic arrays, the most cost-effective implementation is hybrid, not monolithic. Moreover, we show that the most cost-effective interconnection hologram is monolithic.© (1993) COPYRIGHT SPIE--The International Society for Optical Engineering. Downloading of the abstract is permitted for personal use only.