Chein-Wei Jen

On the design automation of the memory-based VLSI architectures for FIR filters

An approach to automating the design of memory-based VLSI architectures for FIR (finite impulse response) filters has been developed. The automation is based on the exploration of the design space and schemes for efficient memory replacement, algorithm formulation, architecture design, and evaluation method. Various schemes and design considerations were integrated to produce a parameterized MBA (memory-based architecture) that can easily be tuned to various hardware-speed requirements. This MBA is characterized by three design parameters. Differently configured MBAs result from specifying different values for these parameters. Hardware-speed evaluation formulas were established based on the required elements in MBAs. These elements include ROM, adders, and shift registers. These formulas and a cell library of a target technology can be used to design an optimally configured MBA by searching for the best values of the design parameters with the aid of a computer. Using the evaluation formulas and the parameterized architecture, an area-minimized architecture can be synthesized under a speed specification. Based on these results, an automatic synthesis too has been developed. >

Low power design for MPEG-2 video decoder

The I/O power consumption in an MPEG-2 decoder is significant because of the wide connection with large capacitances to the frame buffer. To reduce the power dissipation on the memory bus, the Gray code encoding scheme is proposed to increase the correlation of the image data transferred on the bus. The bit switching probability in the re-coded data will then decrease and in turn the bus power consumption will be reduced. Combined with the proposed bus arbitration and scheduling scheme proposed in this paper, 22% reduction of power dissipation may be achieved.

Optimal frame memory and data transfer scheme for MPEG-4 shape coding

An optimal frame memory and data transfer scheme is proposed for MPEG-4 shape coding in embedded systems. The proposed alpha frame buffer scheme contains two approaches. First, a distributed tile-based memory organization is used to efficiently support the time-varying size of alpha plane. Second, a compression scheme is used to reduce the number of memory access to and the size of the alpha frame memory. Under the criteria of MPEG-4 standard, the size of alpha frame memory can be reduced to 50% by introducing a small index table (2.73%-5.08% of the original frame memory size). A coarse assessment shows that the number of memory reference can be reduced to 56.25%. On the other hand, the proposed data transfer scheme combines the run length coding and addressing mode to reduce average data transfer time to 9.39%. Therefore, the shared system bus can be kept as free as possible, which in turn leads to increasing the potentialities of improvement on system performance. Furthermore, this data transfer scheme also helps in accelerating the processing of shape coding.

Computation-effective 3-D graphics rendering architecture for embedded multimedia system

A new architecture is proposed to realize 3-D graphics rendering for an embedded multimedia system. Because only 20% to 83% triangles in the original 3-D object models are visible by simulation, our architecture is designed to eliminate the redundant operations on invisible triangles without image quality loss. It is based on our index rendering and enhanced deferred lighting approach, and it features a dual pipeline rendering architecture. The simulation and analysis results show that this architecture can save up to 63.4% CPU operations compared with traditional architectures.

A Multiplierless Reconfigurable Resizer For Multi-window Image Display

This paper presents a real-time resizing IC that can dynamically reconfigure the multiplierless polyphase CIC (cascaded-integer-comb) filter modules to meet even noninteger resizing ratio. The hardware cost is greatly reduced by using overlap-save based block input and concurrent register reset scheme. The simulated results show that this chip can process four 320/spl times/200 30 frames/sec at 55 MHz clock.

On the bus arbitration for MPEG 2 video decoder

A bus arbitration scheme for the MPEG-2 video decoder VLSI developed by NCTU is proposed in this paper. Compared to the traditional pure stochastic bus scheduling scheme, the internal buffer requirement and bus arbitration overheads are reduced due to the deterministic nature of this strategy. This bus arbitration scheme has been verified using a Verilog simulator and will be implemented in the NCTU MPEG-2 decoder.

The designs of two-level pipelined systolic arrays for recursive digital filters with maximum throughput rate

Presents two-level pipelined systolic arrays for high throughput IIR filters. By combining the look-ahead schemes and the two-level pipelining technique, the VLSI architectures which support the maximum throughput rate and the strategies which make this rate possible are derived. Extending the results concluded from 1-D IIR filters, the authors also present high throughput rate realizations for 2-D IIR filters.<<ETX>>

A low-cost raster engine for video game, multimedia PC and interactive TV

A low-cost Raster Engine (RE) is designed and implemented to improve the performance of 3D computer graphics and image composition application for video games, multimedia PCs and interactive TVs. Three operation modes: Gouraud and Phong shading algorithms, and image composition are incorporated in this chip. Modified digital differential analyzer (DDA), 2-level pipeline, and constant execution time for calculating cos/sup n/ /spl theta/ are proposed as the features of this design. The accelerator is implemented by 0.8 /spl mu/m SPDM CMOS VLSI technology and able to release more then 50% CPU loads. >

The design of two-dimensional FIR and IIR filter architectures for HDTV signal processing

Multiplexers and carry-save-adders are used as the basic cells of designing two-dimensional FIR and IIR filter architectures for HDTV image processing. Compared with the existed design, this architecture can process each sample in eight gate delays without trading with extra hardware. Besides, it has the features of short latency, low cost and is systolic.<<ETX>>

A bit-level scalable median filter using simple majority circuit

A median filtering algorithm based on binary radix is presented. It performs mask-and-set operations and takes the majority at each binary digit. The majority bits thus constitute the median value in the set of binary numbers. A circuit composed of output-wired inverters is used to implement the majority function. Through a buffering inverter, the majority bit comes out in just two inverter delays. A simple design, less hardware and thus faster speed can be achieved. A bit-level scalable median filter architecture using this algorithm is proposed. It works in a pipelined style, is useful in real-time image smoothing, and is suitable for VLSI implementation.<<ETX>>