Chen Chixiao

A 14-bit 200-MS/s time-interleaved ADC with sample-time error calibration

Sample-time error between channels degrades the resolution of time-interleaved analog-to-digital converters (TIADCs). A calibration method implemented in mixed circuits with low complexity and fast convergence is proposed in this paper. The algorithm for detecting sample-time error is based on correlation and widely applied to wide-sense stationary input signals. The detected sample-time error is corrected by a voltage-controlled sampling switch. The experimental result of a 2-channel 200-MS/s 14-bit TIADC shows that the signal-to-noise and distortion ratio improves by 19.1 dB, and the spurious-free dynamic range improves by 34.6 dB for a 70.12-MHz input after calibration. The calibration convergence time is about 20000 sampling intervals.

A capacitive DAC with custom 3-D 1-fF MOM unit capacitors optimized for fast- settling routing in high speed SAR ADCs

Asynchronous successive approximation register (SAR) analog-to-digital converters (ADC) feature high energy efficiency but medium performance. From the point of view of speed, the key bottleneck is the unit capacitor size. In this paper, a small size three-dimensional (3-D) metal—oxide—metal (MOM) capacitor is proposed. The unit capacitor has a capacitance of 1-fF. It shapes as an umbrella, which is designed for fast settling consideration. A comparison among the proposed capacitor with other 3-D MOM capacitors is also given in the paper. To demonstrate the effectiveness of the MOM capacitor, a 6-b capacitive DAC is implemented in TSMC 1P9M 65 nm LP CMOS technology. The DAC consumes a power dissipation of 0.16 mW at the rate of 100 MS/s, excluding a source-follower based output buffer. Static measurement result shows that INL is less than ±1 LSB and DNL is less than ±0.5 LSB. In addition, a 100 MS/s 9-bit SAR ADC with the proposed 3-D capacitor is simulated.

An analog front end with a 12-bit 3.2-MS/s SAR ADC for a power line communication system

This paper presents an analog front end for a power line communication system, including a 12-bit 3.2-MS/s energy-efficient successive approximation register analog-to-digital converter, a positive feedback programmable gain amplifier, a 9.8 ppm/°C bandgap reference and on-chip low-output voltage regulators. A two segment capacitive array structure (6 MSB 5 LSB) composed by split capacitors is designed for the SAR core to save area cost and release reference voltage accuracy requirements. Implemented in the GSMC 0.13 μm 1.5 V/12 V dual-gate 4P6M e-flash process, the analog front end occupies an area of 0.457 mm2 and consumes power of 18.8 mW, in which 1.1 mW cost by the SAR ADC. Measured at 500 kHz input, the spurious-free dynamic range and signal-to-noise plus distortion ratio of the ADC are 71.57 dB and 60.60 dB respectively, achieving a figure of merit of 350 fJ/conversion-step.

200MS/s 10bit SAR ADC with 1.5bit redundant acceleration

This paper presents a low power 10-bit 200MS/s successive approximation register analog-to-digital converter (SAR ADC) with 1.5bit redundant acceleration. In this design, technique of 1.5bit redundant acceleration is used in second bit of SAR ADC, which reduces the building waiting time of first bit without other comparison clock consumption. To realize low power, a brand-new 3-D 1-fF MOM unit capacitor is used as basic capacitor cell of capacitor array. The design is fabricated in TSMC IP9M 65nm LP CMOS technology. At the same sampling rates of 200MS/s, the simulation of proposed SAR ADC achieves an ENOB of 9.84bit, an SNDR of 59.8dB, an SFDR of 67.5dB and power consumption of 0.58mW under Nyquist sampling. The FOM of the SAR ADC is low to 2.83fJ/conv.

100MS/s 9-bit 0.43mW SAR ADC with custom capacitor array

This paper presents a low power 9-bit 100MS/s successive approximation register analog-to-digital converter (SAR ADC) due to the custom capacitor array. In this capacitor array, a brand-new 3-D 1-fF MOM unit capacitor is used as basic capacitor cell. A beneficial improvement to capacitor array structure makes some difference too. The design is fabricated in TSMC IP9M 65nm LP CMOS technology. At the same sampling rates of 100MS/s, the layout simulation of proposed SAR ADC achieves an ENOB of 8.54bit, an SNDR of 53.15dB, an SFDR of 63.14dB and power consumption of 0.43mW under Nyquist sampling. The FOM of the SAR ADC is low to 8.63fJ/conv.

Robust design of a 500-MS/s 10-bit triple-channel current-steering DAC in 40 nm CMOS

A 500-MS/s 10-bit triple-channel current-steering DAC in 40 nm 1P8M CMOS advanced technology is proposed. The central symmetry random walk scheme is applied for current source arrays to avoid mismatching effects in nano-CMOS design. The high-speed latch drivers can be self-adaptively connected to switches in different voltage domains. The experimental data shows that the maximum DNL and INL are 0.42 LSB and 0.58 LSB. The measured SFDR at 1.7 MHz output signal is 58.91 dB, 58.53 dB and 56.98 dB for R/G/B channels, respectively. The DAC has good static and dynamic performance despite the single-ended output. The average rising time and falling time of three channels are 0.674 ns and 0.807 ns. The analog/digital power supply is 3.3 V/1.1 V. This triple-channel DAC occupies 0.5656 mm2.