Chen-Han Tsai

Analysis and architecture design of an HDTV720p 30 frames/s H.264/AVC encoder

H.264/AVC significantly outperforms previous video coding standards with many new coding tools. However, the better performance comes at the price of the extraordinarily huge computational complexity and memory access requirement, which makes it difficult to design a hardwired encoder for real-time applications. In addition, due to the complex, sequential, and highly data-dependent characteristics of the essential algorithms in H.264/AVC, both the pipelining and the parallel processing techniques are constrained to be employed. The hardware utilization and throughput are also decreased because of the block/MB/frame-level reconstruction loops. In this paper, we describe our techniques to design the H.264/AVC video encoder for HDTV applications. On the system design level, in consideration of the characteristics of the key components and the reconstruction loops, the four-stage macroblock pipelined system architecture is first proposed with an efficient scheduling and memory hierarchy. On the module design level, the design considerations of the significant modules are addressed followed by the hardware architectures, including low-bandwidth integer motion estimation, parallel fractional motion estimation, reconfigurable intrapredictor generator, dual-buffer block-pipelined entropy coder, and deblocking filter. With these techniques, the prototype chip of the efficient H.264/AVC encoder is implemented with 922.8 K logic gates and 34.72-KB SRAM at 108-MHz operation frequency.

Survey on Block Matching Motion Estimation Algorithms and Architectures with New Results

Abstract.Block matching motion estimation is the heart of video coding systems. During the last two decades, hundreds of fast algorithms and VLSI architectures have been proposed. In this paper, we try to provide an extensive exploration of motion estimation with our new developments. The main concepts of fast algorithms can be classified into six categories: reduction in search positions, simplification of matching criterion, bitwidth reduction, predictive search, hierarchical search, and fast full search. Comparisons of various algorithms in terms of video quality and computational complexity are given as useful guidelines for software applications. As for hardware implementations, full search architectures derived from systolic mapping are first introduced. The systolic arrays can be divided into inter-type and intra-type with 1-D, 2-D, and tree structures. Hexagonal plots are presented for system designers to clearly evaluate the architectures in six aspects including gate count, required frequency, hard-ware utilization, memory bandwidth, memory bitwidth, and latency. Next, architectures supporting fast algorithms are also reviewed. Finally, we propose our algorithmic and architectural co-development. The main idea is quick checking of the entire search range with simplified matching criterion to globally eliminate impossible candidates, followed by finer selection among potential best matched candidates. The operations of the two stages are mapped to the same hardware for resource sharing. Simulation results show that our design is ten times more area-speed efficient than full search architectures while the video quality is competitively the same.

A 1.3TOPS H.264/AVC single-chip encoder for HDTV applications

An H.264/AVC encoder is implemented on a 31.72mm/sup 2/ die with 0.18/spl mu/m CMOS technology. A four-stage macroblock pipelined architecture encodes 720p 30f/s HDTV videos in real time at 108MHz. The encoded video quality is competitive with reference software requiring 3.6TOPS on a general-purpose processor-based platform.

Architecture design of area-efficient SRAM-based multi-symbol arithmetic encoder in H.264/AVC

The first SRAM-based multi-symbol arithmetic encoder was proposed in this paper. Since several SRAM problems arise in this highly data-dependent operation, four methods were introduced to make it feasible. Based on data-forwarding architecture, modular banks with throw-backward/catch-forward and read/write isolation greatly enhanced the throughput. Our SRAM-based approach was implemented with 29%-35% of area compared to register-based design. Moreover, different throughput required in various applications could be attained by changing the number of SRAM banks. The proposed SRAM-based multi-symbol arithmetic encoder achieved high throughput and low cost at the same time

Algorithm analysis and architecture design for HDTV applications - a look at the H.264/AVC video compressor system

In this article, we suggest some techniques to design the H.264/AVC video coding system for HDTV applications. The design exploration is made according to software profiling. The design considerations of system scheduling and pipelining are discussed followed by the architecture optimization of the significant modules. The efficient H.264/AVC video coding system is achieved by combining these techniques

Frame-parallel design strategy for high definition B-frame H.264/AVC encoder

High Definition (HD) H.264/AVC video compression is the emerging necessity on nowadays home entertainment environment and so on. However, Although B-frame coding scheme provides better quality, only P-frame encoders are presented due to too high complexity and memory requirement. In this paper, a frame-parallel encoding scheme based on B-frames data independency is proposed. It can largely reduce the system memory bandwidth and improve the processing capability. Then, the proposed IME and FME scheduling can further enhance the hardware utilization for frame-parallel scheme. Finally, a case study is given to show that the proposed scheme can largely reduce 66% system bandwidth compared to direct implementation from previous P-frame encoder.

A flexible fully hardwired CABAC encoder for UHDTV H.264/AVC high profile video

In this paper, a flexible CABAC encoder architecture for H.264/AVC encoder applications up to UHDTV (7680×4320) resolution is proposed. Stages of CABAC encoding are analyzed and a generalized CABAC architecture is designed. The parallel binarizer and context modeler (BCM) and multi-symbol binary arithmetic coder (MSBAC) is coupled together by a variable throughput buffer and packers (VTBAP) for throughput matching. Syntax elements (SEs) are analyzed thoroughly and various SEs processing engines are proposed to achieve parallelism for performance with high degree of flexibility for CABAC designers. Special attentions have been paid to the feeding of SEs into BCM that is not discussed in most other works. Without the bubble-free access control and the bubble-free feeding of SEs, the high throughput of BCM and MSBAC engine will not be possible to integrate with the rest of the encoder engine, otherwise external pre-processing has to be applied for SEs feeding. Flexibilities of architecture and level of parallelism are incorporated into a CABAC auto generating scheme that can produce the CABAC configurations according to user requirements. Towards a 0.13 μm CMOS technology, the highest performance design generated by the automatic generation scheme can encode 4.86 bins per cycle on the average, and it provides a throughput of 1234 Mbin/s. The proposed CABAC encoder architecture has been integrated into a H.264/AVC encoder of a multimedia SoC successfully.

Novel Configurable Architecture of ML-Decomposed Binary Arithmetic Encoder for Multimedia Applications

A novel architecture of ML-decomposed binary arithmetic coder is proposed. Through the analysis of previous designs, the traditional processing unit is divided into two parts, MPS encoder and LPS encoder. With different arrangements of these two basic components, we develop two types of ML-decomposed structures. To increase the throughput of arithmetic coding, ML cascade architecture puts the coders in serial, while throughput-selection architecture offers several choices in parallel. Their design methodologies are described in this paper. Both methods achieve very high throughput, more than 800 M symbols/sec. And they are configurable and extensible to supply a wide range of specifications. Moreover, the proposed architecture can be used in binary arithmetic coding of various video and image standards.

Algorithm and architecture optimization for full-mode encoding of H.264/AVC intra prediction

In this paper, we designed a four-parallel intra prediction architecture applied with four optimization schemes. Category-level interleaved scheme (CLIS) eliminates the bubble cycles of 14MB reconstruction. Mode-level scheduling (MLS) and early data preparation scheme (EDPS) rearrange the processing sequence of intra modes. The hardware resource of earlier low-complexity modes is used to deal with the computation of later high-load modes. Not only the hardware utilization is increased but the processing cycles is reduced. Furthermore, stage-level partial distortion elimination (SLPDE) is induced to skip the calculation of unnecessary intra modes. The architecture has been integrated into an H.264/AVC baseline encoder for HDTV applications and has been verified to be feasible under system consideration.

Efficient Hardware Architecture for Large Disparity Range Stereo Matching Based on Belief Propagation

This paper introduces an efficient hardware architecture for the belief propagation(BP) algorithm especially for large disparity range stereo matching applications. BP is a popular global optimization algorithm for labelling problems which is hardware friendly. There are few types of research focus on BP implementation in large disparity range stereo matching problem since traditional belief propagation hardware implementations suffer from a server trade-off between hardware efficiency and short critical path while the disparity range is larger than 64. In this paper, we eliminate the redundancy of previous BP implementation and propose an efficient architecture without introducing any delay overhead which is more suitable for large disparity range cases. As a result, the hardware complexity is reduced from O(L2) to O(Llog2 L), where L is the disparity range. We use a time-area term to demonstrate the trade-off between various architectures, results show that the proposed one can reach 49:6% and 71:2% reduction compared to the state-of-the-art implementation with disparity ranges 64 and 128 respectively.