Chenchang Zhan

A low-complexity fast-locking digital PLL with multi-output bang-bang phase detector

This paper presents a locking-accelerated DPLL based on multi-output bang-bang phase detector (MOBBPD) with reused most significant bits (MSBs). The bang-bang structure has simple implementation by eliminating the sensitive time-to-digital converter (TDC), while MOBBPD allows for reduced loop locking-time due to the multi-output. To further accelerate the loop locking, a scheme of reusing the MSBs is proposed to signify the large phase-difference at the early stage of lock acquisition, hence reducing the phase difference quickly. The low complexity of the design is maintained due to the simple structure. The proposed DPLL is designed using a 0.18-μm CMOS process. It generates an output clock frequency range of 1–2.2 GHz with 7.8–17.2 MHz input reference frequency. The power consumption is 5.1 mW while the locking speed is improved by around 20 times improvement compared to without reusing the MSBs.

An ultra-low power CMOS subthreshold voltage reference without requiring resistors or BJTs

This paper presents a novel ultra-low power voltage reference operational from supply voltage down to less than 0.9V. In the proposed reference circuit, the PTAT voltage is generated by feeding the leakage current of a zero-Vgs NMOS transistor to two diode-connected NMOS transistors, both of which are in subthreshold region; while the CTAT voltage is created by using the body-diodes of another NMOS transistor. Consequently, low-voltage, low-power operation can be achieved without requiring resistors or BJTs, hence with small chip area consumption. The proposed circuit is designed in a 0.18-μm process. Simulation results show that it is capable of providing an 808mV reference voltage with 10ppm/°C from −30°C–125°C even with only 900mV supply voltage. Moreover, the typical power consumption is only 10nW.

Analysis and design of a current-mode bandgap reference with high power supply ripple rejection

In this paper, a current-mode bandgap reference (BGR) circuit with cascode current mirrors and improved frequency compensation for achieving high power supply ripple rejection (PSRR) is presented. By slightly modifying a conventional frequency compensation scheme, the PSRR of the BGR is significantly enhanced. PSRRs of the BGR with the two different compensation techniques have been formulated and verified. Moreover, design considerations are presented, taking into account the critical parasitic capacitors effect in PSRR. To our knowledge, this is the first time in the literature of explicitly demonstrating how the PSRR of a BGR is improved due to the frequency compensation. The feedback loop stability is also analyzed. The measured PSRR of an example BGR using the modified compensation fabricated in a standard 0.18-m CMOS process is 77dB and 62dB at 1kHz, and 100kHz, respectively, with more than 40dB improvement at the high frequency ranges over the design with the classical compensation.

Design of high-PSRR current-mode bandgap reference with improved frequency compensation

In this paper, a current-mode bandgap reference (BGR) circuit with cascode current mirrors and improved frequency compensation for achieving high power supply ripple rejection (PSRR) is presented. By slightly modifying a conventional frequency compensation scheme, the PSRR of the BGR is significantly enhanced. PSRRs of the BGR with the two different compensation techniques have been formulated. To our knowledge, this is the first time in the literature of explicitly demonstrating how the PSRR is improved due to the frequency compensation. The feedback loop stability is also analyzed. The simulated PSRR of an example BGR using the modified compensation in a 0.18-μm CMOS process is -108 dB, -68 dB, and -61 dB at DC, 10 kHz, and 10 MHz, respectively, with more than 40dB improvement at certain high frequency ranges over the design with the classical compensation.