Cheng-Cheng Yen

Investigation and Design of On-Chip Power-Rail ESD Clamp Circuits Without Suffering Latchup-Like Failure During System-Level ESD Test

On-chip power-rail electrostatic discharge (ESD) protection circuit designed with active ESD detection function is the key role to significantly improve ESD robustness of CMOS integrated circuits (ICs). Four power-rail ESD clamp circuits with different ESD-transient detection circuits were fabricated in a 0.18-mum CMOS process and tested to compare their system-level ESD susceptibility, which are named as power-rail ESD clamp circuits with typical RC-based detection, PMOS feedback, NMOS+PMOS feedback, and cascaded PMOS feedback in this work. During the system-level ESD test, where the ICs in a system have been powered up, the feedback loop used in the power-rail ESD clamp circuits provides the lock function to keep the ESD-clamping NMOS in a ldquolatch-onrdquo state. The latch-on ESD-clamping NMOS, which is often drawn with a larger device dimension to sustain high ESD level, conducts a huge current between the power lines to perform a latchup-like failure after the system-level ESD test. A modified power-rail ESD clamp circuit is proposed to solve this problem. The proposed power-rail ESD clamp circuit can provide high enough chip-level ESD robustness, and without suffering the latchup-like failure during the system-level ESD test.

On-Chip Transient Detection Circuit for System-Level ESD Protection in CMOS Integrated Circuits to Meet Electromagnetic Compatibility Regulation

A new on-chip transient detection circuit for system-level electrostatic discharge (ESD) protection is proposed. The circuit performance to detect different positive and negative fast electrical transients has been investigated by the HSPICE simulator and verified in a silicon chip. The experimental results in a 0.13-m CMOS integrated circuit (IC) have confirmed that the proposed on-chip transient detection circuit can be used to detect fast electrical transients during the system-level ESD events. The proposed transient detection circuit can be further combined with the power-on reset circuit to improve the immunity of the CMOS IC products against system-level ESD stress.

Transient-to-Digital Converter for System-Level Electrostatic Discharge Protection in CMOS ICs

A new on-chip RC-based transient detection circuit for system-level electrostatic discharge (ESD) protection is proposed, which can detect fast electrical transients during the system-level ESD test. A novel on-chip transient-to-digital converter composed of four RC-based transient detection circuits and four different RC filter networks has been successfully designed and verified in a 0.18- mum CMOS process with 3.3-V devices. The output digital thermometer codes of the proposed on-chip transient-to-digital converter correspond to different ESD voltages under system-level ESD tests. The proposed on-chip transient-to-digital converter can be further combined with firmware cooperation to provide an effective solution to solve the system-level ESD protection issue in microelectronic systems equipped with CMOS ICs.

The Effect of IEC-Like Fast Transients on

Four power-rail electrostatic-discharge (ESD) clamp circuits with different ESD-transient detection circuits have been fabricated in a 0.18-mum CMOS process to investigate their susceptibility against electrical fast-transient (EFT) tests. Under EFT tests, where the integrated circuits in a microelectronic system have been powered up, the feedback loop used in the power-rail ESD clamp circuits may lock the ESD-clamping NMOS in a ldquolatch-onrdquo state. Such a latch-on ESD-clamping NMOS will conduct a huge current between the power lines to perform a latchuplike failure after EFT tests. A modified power-rail ESD clamp circuit has been proposed to solve this latchuplike failure and to provide a high-enough chip-level ESD robustness.

RC

Four different on-chip power-rail electrostatic discharge (ESD) clamp circuits have been designed to investigate their susceptibility to electrical fast transient (EFT) test. From the experimental results, the feedback loop in two kinds of on-chip power-rail ESD clamp circuits provides the lock function to perform a latchup-like failure after the EFT test. The re-design solution will be developed to overcome this issue to meet the regulation of EFT/EMC test.

-Triggered ESD Power Clamps

The occurrence of transient-induced latchup (TLU) in CMOS integrated circuits (ICs) under electrical fast-transient (EFT) tests is studied. The test chip with the parasitic silicon-controlled-rectifier (SCR) structure fabricated by a 0.18-mum CMOS process was used in EFT tests. For physical mechanism characterization, the specific ldquoswept-backrdquo current caused by the minority carriers stored within the parasitic PNPN structure of CMOS ICs is the major cause of TLU under EFT tests. Different types of board-level noise filter networks are evaluated to find their effectiveness for improving the immunity of CMOS ICs against TLU under EFT tests. By choosing the proper components in each noise filter network, the TLU immunity of CMOS ICs against EFT tests can be greatly improved.

Unexpected failure in power-rail ESD clamp circuits of CMOS integrated circuits in microelectronics systems during electrical fast transient (EFT) test and the re-design solution

A new on-chip 4-bit transient-to-digital converter for system-level electrostatic discharge (ESD) protection design is proposed. The proposed converter is designed to detect ESD-induced transient disturbances and transfer different ESD voltages into digital codes under system-level ESD tests. The experimental results in a 0.13- μm CMOS integrated circuit with 1.8-V devices have confirmed the detection function and digital output codes. The proposed on-chip transient-to-digital converter can be codesigned with firmware operations to effectively enhance immunity of display systems against system-level ESD stresses.

Transient-Induced Latchup in CMOS ICs Under Electrical Fast-Transient Test

A new transient detection circuit for on-chip protection design against system-level electrical-transient disturbance is proposed in this paper. The circuit function to detect positive or negative electrical transients under system-level electrostatic-discharge (ESD) and electrical-fast-transient (EFT) testing conditions has been investigated by HSPICE simulation and verified in silicon chip. The experimental results in a 0.18-μm complementary-metal-oxide-semiconductor (CMOS) process have confirmed that the new proposed on-chip transient detection circuit can successfully memorize the occurrence of system-level electrical-transient disturbance events. The output of the proposed on-chip transient detection circuit can be used as a firmware index to execute the system recovery procedure. With hardware/firmware codesign, the transient disturbance immunity of microelectronic products equipped with CMOS integrated circuits under system-level ESD or EFT tests can be significantly improved.

New 4-Bit Transient-to-Digital Converter for System-Level ESD Protection in Display Panels

A new transient detection circuit against electrical fast transient (EFT) disturbance is proposed for display panel protection. The circuit function to detect positive or negative electrical transients under EFT tests has been investigated in HSPICE simulation and verified in silicon chip. The output of the proposed transient detection circuit can be used as a firmware index to execute system automatic recovery operation. With hardware/firmware co-design, the immunity of display panel against transient disturbance under EFT tests can be significantly improved.

New Transient Detection Circuit for On-Chip Protection Design Against System-Level Electrical-Transient Disturbance

A new on-chip CR-based electrostatic discharge (ESD) detection circuit for system-level ESD protection design is proposed in this work. The circuit performance to detect positive or negative electrical transients generated by system-level ESD tests has been analyzed in HSPICE simulation and verified in silicon chip. The experimental results in a 0.13-µm CMOS process have confirmed that the proposed detection circuit can detect ESD-induced transient disturbance during system-level ESD zapping. The detection results can be used as system recovery firmware index to improve the immunity of CMOS IC products against system-level ESD stress.