Chengen Yang

Product Code Schemes for Error Correction in MLC NAND Flash Memories

Error control coding (ECC) is essential for correcting soft errors in Flash memories. In this paper we propose use of product code based schemes to support higher error correction capability. Specifically, we propose product codes which use Reed-Solomon (RS) codes along rows and Hamming codes along columns and have reduced hardware overhead. Simulation results show that product codes can achieve better performance compared to both Bose-Chaudhuri-Hocquenghem codes and plain RS codes with less area and low latency. We also propose a flexible product code based ECC scheme that migrates to a stronger ECC scheme when the numbers of errors due to increased program/erase cycles increases. While these schemes have slightly larger latency and require additional parity bit storage, they provide an easy mechanism to increase the lifetime of the Flash memory devices.

Enhancing the Reliability of STT-RAM through Circuit and System Level Techniques

Spin torque transfer random access memory (STT-RAM) is a promising memory technology because of its fast read access, high storage density, and very low standby power. These memories have reliability issues that need to be better understood before they can be adopted as a mainstream memory technology. In this paper, we first study the causes of errors for a single STT memory cell. We see that process variations and variations in the device geometry affect their failure rate and develop error models to capture these effects. Next we propose a joint technique based on tuning of circuit level parameters and error control coding (ECC) to achieve very high reliability. Such a combination allows the use of weaker ECC with smaller overhead. For instance, we show that by applying voltage boosting and write pulse width adjustment, the error correction capability (t) of ECC can be reduced from t=11 to t=3 to achieve a block failure rate (BFR) of 10-9.

Data storage time sensitive ECC schemes for MLC NAND Flash memories

Errors in MLC NAND Flash can be classified into retention errors and program interference (PI) errors. While retention errors are dominant when the data storage time is greater than 1 day, PI errors are dominant for short data storage times. Furthermore these two types of errors have different probabilities of 0->1 or 1->0 bit flips. We utilize the characteristics of the two types of errors in the development of ECC schemes for applications that have different storage times. In both cases, we first apply Gray coding and 2-bit interleaving. The corresponding most significant bit (MSB) and least significant bit (LSB) sub-page has only one type of dominating error (0->1 or 1->0). Next we form a product code using linear block code along rows and even parity check along columns to detect all the possible error locations. We develop an algorithm to choose errors among the possible error locations based on the dominant error type. Performance simulation and hardware implementation results show that the proposed solutions have the same performance as BCH codes with larger error correction capability but with significantly lower hardware overhead. For instance, for a 2KB MLC Flash used in long storage time applications, the proposed ECC scheme has 50% lower energy and 60% lower decoding latency compared to the BCH scheme.

Improving reliability of non-volatile memory technologies through circuit level techniques and error control coding

Non-volatile resistive memories, such as phase-change RAM (PRAM) and spin transfer torque RAM (STT-RAM), have emerged as promising candidates because of their fast read access, high storage density, and very low standby power. Unfortunately, in scaled technologies, high storage density comes at a price of lower reliability. In this article, we first study in detail the causes of errors for PRAM and STT-RAM. We see that while for multi-level cell (MLC) PRAM, the errors are due to resistance drift, in STT-RAM they are due to process variations and variations in the device geometry. We develop error models to capture these effects and propose techniques based on tuning of circuit level parameters to mitigate some of these errors. Unfortunately for reliable memory operation, only circuit-level techniques are not sufficient and so we propose error control coding (ECC) techniques that can be used on top of circuit-level techniques. We show that for STT-RAM, a combination of voltage boosting and write pulse width adjustment at the circuit-level followed by a BCH-based ECC scheme can reduce the block failure rate (BFR) to 10–8. For MLC-PRAM, a combination of threshold resistance tuning and BCH-based product code ECC scheme can achieve the same target BFR of 10–8. The product code scheme is flexible; it allows migration to a stronger code to guarantee the same target BFR when the raw bit error rate increases with increase in the number of programming cycles.

Hierarchical modeling of Phase Change memory for reliable design

As CMOS based memory devices near their end, memory technologies, such as Phase Change Random Access Memory (PRAM), have emerged as viable alternatives. This work develops a hierarchical modeling framework that connects the unique device physics of PRAM with its circuit and state transition properties. Such an approach enables design exploration at various levels in order to optimize the performance and yield. By providing a complete set of compact models, it supports SPICE simulation of PRAM in the presence of process variations and temporal degradation. Furthermore, this work proposes a new metric, State Transition Curve (STC) that supports the assessment of other performance metrics (e.g., power, speed, yield, etc.), helping gain valuable insights on PRAM reliability.

Flexible product code-based ECC schemes for MLC NAND Flash memories

Error control coding (ECC) is essential for correcting soft errors in Flash memories. In such memories, as the number of erase/program cycles increases over time, the number of errors increases. In this paper we propose a flexible product code based ECC scheme that can support ECC of higher strength when needed. Specifically, we propose product codes which use Reed-Solomon (RS) codes along rows and Hamming codes along columns. When higher ECC is needed, the Hamming code along columns is replaced by two shorter Hamming codes. For instance, when the raw bit error rate increases from 2.2∗10−3 to 4.0∗10−3, the proposed ECC scheme migrates from RS(127, 121) along rows and Hamming(72,64) along columns to RS(127, 121) along rows and two Hamming(39, 32) along columns to achieve the same BER of 10−6. While the resulting implementation has 12% higher decoding latency, it increases the lifetime of the device significantly.

Multi-Tiered Approach to Improving the Reliability of Multi-Level Cell PRAM

Phase change RAM (PRAM) is a promising memory technology because of its fast read access time, high storage density and very low standby power. Multi-level Cell (MLC) PRAM which has been introduced to further improve the storage density, comes at a price of lower reliability. This paper focuses on a cost-effective solution for improving the reliability of MLC-PRAM. As the first step, we study in detail the causes of hard and soft errors and develop error models to capture these effects. Next we propose a multi-tiered approach that spans architecture, circuit and system levels to increase the reliability. At the architecture level, we use a combination of Gray code encoding and 2-bit interleaving to partition the errors so that a lower strength error correction coding (ECC) can be used for half of the bits that are in the odd block. We use sub block flipping and threshold resistance tuning to reduce the number of errors in the even block. For even higher reliability, we use a simple BCH based ECC on top of these techniques. We show that the propose multi-tiered approach enables us to use a low cost ECC with 2-error correction capability (t=2) instead of one with t=8 to achieve a block failure rate of 10-8.

Compact modeling of STT-MTJ for SPICE simulation

STT-MTJ is a promising device for future high-density and low-power integrated systems. To enable design exploration of STT-MTJ, this paper presents a fully compact model for efficient SPICE simulation. Derived from the fundamental LLG equation, the new model consists of RC elements that are closed-form solutions of device geometry and material properties. They support transient SPICE simulations, providing necessary details beyond the macromodel. The accuracy is validated with numerical results and published data.

Low cost ECC schemes for improving the reliability of DRAM+PRAMMAIN memory systems

Hybrid memory, where the DRAM acts as a buffer to the PRAM, is a promising configuration for main memory systems. It has the advantages of fast access time, high storage density and very low standby power. However, it also has reliability issues that need to be addressed. This paper focuses on low cost Error Control Coding (ECC)-based schemes for improving the reliability of hybrid memory. We propose three candidate systems that all guarantee block failure rate of 10-8 but differ in whether the DRAM and/or PRAM data get coded and the strength of the corresponding ECC code. The candidate systems are evaluated with respect to lifetime, Instruction Per Cycle (IPC) and energy. We show that (1) at lower Data Storage Time (DST), the proposed system which has different ECC schemes for DRAM and PRAM has the longest lifetime and one of the highest IPC; (2) at higher DST, stronger ECC codes are necessary for all the systems and longer lifetime can be achieved at the cost of decrease in IPC.