Chenyuan Zhao

Spike-Time-Dependent Encoding for Neuromorphic Processors

This article presents our research towards developing novel and fundamental methodologies for data representation using spike-timing-dependent encoding. Time encoding efficiently maps a signals amplitude information into a spike time sequence that represents the input data and offers perfect recovery for band-limited stimuli. In this article, we pattern the neural activities across multiple timescales and encode the sensory information using time-dependent temporal scales. The spike encoding methodologies for autonomous classification of time-series signatures are explored using near-chaotic reservoir computing. The proposed spiking neuron is compact, low power, and robust. A hardware implementation of these results is expected to produce an agile hardware implementation of time encoding as a signal conditioner for dynamical neural processor designs.

Making neural encoding robust and energy efficient: an advanced analog temporal encoder for brain-inspired computing systems

Neural encoder is one of the key components in neuromorphic computing systems, whereby sensory information is transformed into spike coded trains. The design of temporal encoder has attracted a widespread attention in the field of neuromorphic computing in the past few years. The information in the temporal encoding scheme with inter-spike intervals can arise from correlations between spike times, which could not be incorporated in the traditional rate encoding scheme. In this paper, we propose a robust and energy efficient analog implementation of the spiking temporal encoder. We pattern the neural activities across multiple timescales and encode the sensory information using time dependent temporal scales. The concept of iteration structure is introduced to construct a neural encoder that greatly increases the information process ability of the proposed temporal encoder. Integrated with iteration technique and operational-amplifier-free design, the error rate of the output temporal codes is reduced to an extremely low level. A lower sampling rate accompanied by additional verification spikes is introduced in the schemes, which significantly reduces the power consumption of the encoding system. To the best of our knowledge, our proposed neuron circuit is the first analog hardware implementation of the neural encoder that could present the sensory data using inter-spike interval temporal encoding scheme. The simulation and measurement results show the proposed temporal encoder exhibits not only energy efficiency but also high accuracy.

Neuromorphic encoding system design with chaos based CMOS analog neuron

Neuromorphic computing is a novel paradigm that inspired from the dynamic behavior of the biological brain. The encoding capability plays a vital role in information processing, especially for neural network based systems. In this paper, a compact, low power, and robust spiking-time-dependent encoder is designed with an accommodative Leaky Integrate and Fire (LIF) model based neuron cluster and a chaotic circuit with ring oscillators. Novel and fundamental methodologies, which represent data by using spike timing dependent encoding, has been developed. The information in signal amplitude has been mapped into a spike time sequence efficiently by time encoding, which represents the input data and offers perfect recovery for band limited stimuli. Time dependent temporal scales have been adopted to pattern the neural activities across multiple timescales and encode the sensory information. Furthermore, chaotic circuit based Pseudorandom Time Series Generator (PTSG) is designed to generate sampling clock. High resolution is provided with chaotic based sampling in the proposed encoding circuit. Detailed post layout simulation results and analysis of the designed circuit are presented.

Low power CMOS power amplifier design for RFID and the Internet of Things

Designing power amplifiers with low power consumption, high efficiency and integration is an important topic with significant impact on communication and circuit research areas. In order to make transceivers more powerful with lower cost and higher integration, a CMOS power amplifier working from 3.5GHz to 4.5GHz is proposed. Cascode driver stage is adopted to give the power amplifier high output gain ability. The output stage is designed as Class A, which makes the proposed power amplifier in a significantly high linearity level. Furthermore, this paper gives a comparative study of the performance of different power amplifier classes. Simulation results show that the proposed power amplifier has 31.2% more power added efficiency (PAE) and 12.6dB output power gain, respectively. The proposed power amplifier has high linearity and efficiency, which are suitable for Radio Frequency Identification (RFID) and Internet of Things (IoT) applications.

Novel Spike based Reservoir Node Design with High Performance Spike Delay Loop

With the emerging cutting-edge semiconductor nanotechnologies, reservoir computing has shifted the focus from software implementation towards hardware and optical implementations over the last few decades. Nowadays, in the field of reservoir computing, pure analog implementation with the employment of CMOS nanotechnology has attracted a worldwide attention. In this paper, we introduce a spike-based analog reservoir node with compact delay performing at extremely high accuracy. The detailed work on this novel spike processor working in near chaotic condition is presented and analyzed. Furthermore, we announce a novel class of spike-based delay loop which enables the pure spike implementation of reservoir computing. The simulation results demonstrated that our delay loop possesses exceptionally high accuracy of 99.24% and gain-hold property without adopting any kind of amplifiers. Our proposed reservoir node has shown the potential of transforming spike signals to a high-dimensional state space.

Energy Efficient Spiking Temporal Encoder Design for Neuromorphic Computing Systems

Neuromorphic computing hardware has undergone a rapid development and progress in the past few years. One of the key components in neuromorphic computing systems is the neural encoder which transforms sensory information into spike trains. In this paper, both rate encoding and temporal encoding schemes are discussed. Two novel temporal encoding schemes, parallel and iteration, are presented. The power consumption of the encoder has been significantly reduced by combing the iteration encoding and low sampling rate in advanced complementary metal-oxide semiconductor (CMOS) nano-technology. Both the simulation and measurement results show the accuracy and efficiency of the proposed encoding circuits. The proposed iteration encoder has immediate applicability as a general purpose input encoder for a reservoir computing system.

Channel estimation in wireless OFDM systems using reservoir computing

Reservoir Computing (RC) is a recent neurologically inspired concept for processing time dependent data that lends itself particularly well to hardware implementation by using the device physics to conduct information processing. In this paper, we apply RC to channel estimation in Orthogonal Frequency Division Multiplexing (OFDM) systems. Due to the multipath propagation environment between a transmitter and receiver, the received signal undergoes attenuation, time delay and phase shift. For mitigating these random effects and decoding the transmitted signal at the receiver, accurate channel estimation is vital. Statistical approaches for channel estimation assume that accurate channel information is available at the receiver. However, the time-variance of the channel complicates the channel estimation process by making the current estimation outdated. Recurrent Neural Networks (RNNs), which are analogous to the functioning of the human brain, are therefore utilized for channel prediction. Training algorithms for RNNs are categorized as gradient-descent methods, which often results in high computational complexity and leads to non-convergence due to the presence of bifurcations. In this paper, an Echo State Network (ESN), which is a class of RC approach, has been used for training a RNN to estimate the channel state information. Using this approach, the training and hence, the implementation complexity is significantly reduced. Simulation results show significant improvement in channel estimation accuracy for the proposed method.

Enabling Sustainable Cyber Physical Security Systems through Neuromorphic Computing

As the novel paradigm in the field of machine learning, reservoir computing possesses exceptional performance, e.g., energy efficiency, in tasks in which the traditional von Neumann computing systems cannot incorporate. This makes reservoir computing an ideal candidate to enable the sustainable development of cyber-physical systems (CPS). In the realm of CPS, the tight interaction among physical objects places security threats under the spotlight of attention. For such systems, especially the power grid network, false data injection could potentially lead to catastrophic consequences such as blackouts in large geographical areas. In this paper, we will introduce a reservoir computing architecture, the delayed feedback system, and apply the reservoir computing architecture for anomaly detection. To be specific, detailed design of the three imperative components in the delayed feedback system will be discussed and the corresponding energy efficiency performance will be analyzed. The application of the reservoir computing architecture to anomaly detection in a smart grid network will be introduced.

Analog hardware implementation of spike-based delayed feedback reservoir computing system

The rate of enhancement is starting to saturate and slow down which indicates the end of Moores prediction due to the fundamental performance limits of the chips. The need of breaking through the barrier has directed researchers into several directions, for instance, novel computing architecture. Reservoir computing, a novel concept in the field of machine learning, has emerged over the past few years. Combined the memory and spatio-temporal processing of recurrent neural networks, reservoir computing possesses the capability of processing temporal information. In this paper, we present an analog hardware implementation of delayed feedback reservoir computing system. We build a new class of computationally efficient spike timing-dependent encoders and delay-based reservoirs within reservoir networks. This approach allows us to avoid using power-consuming analog-to-digital converters (ADCs) and operational amplifiers (Op-AMPs), resulting in significant savings in power requirements and design area.

Interspike-Interval-Based Analog Spike-Time-Dependent Encoder for Neuromorphic Processors

Von Neumann bottleneck, which refers to the limited throughput between the CPU and memory, has already become a major factor hindering the technical advances of computing systems. In recent years, neuromorphic systems have started to gain the increasing attentions as compact and energy-efficient computing platforms. As one of the most crucial components in the neuromorphic computing systems, neural encoder transforms the stimulus (input signals) into spike trains. In this paper, we adapt the temporal encoding scheme of interspike intervals (ISIs) and present an analog temporal neural encoder with its verification and recovery schemes. The proposed neural encoder allows efficient mapping of signal amplitude information into a spike-time sequence that represents the input data and offers perfect recovery for band-limited stimuli. With the novel iterative structure, the number of spikes increases exponentially with the number of neurons. From the measurements obtained from the fabricated neural encoder chip, our temporal encoder with ISI encoding is proved to be robust and error tolerant.