Chenyue Ma

Zero-Mask Contact Fuse for One-Time-Programmable Memory in Standard CMOS Processes

This letter describes the formation of one-time-programmable (OTP) memory using standard contact fuse and polysilicon diode in a standard CMOS technology. Programming of the contact fuse is achieved by applying a high current pulse to destroy the contact. Compared with other existing OTP technologies, the proposed approach has the advantage of zero additional mask, no additional processing step, compact structure, and low programming voltage. The described OTP has been demonstrated in a 0.18-μm CMOS technology from TSMC with a cell size of 2.33 μm2 . The contact fuse can be programmed with a voltage of 3 V and a current of 2.4 mA.

A Charge-Based Model for Long-Channel Cylindrical Surrounding-Gate MOSFETs From Intrinsic Channel to Heavily Doped Body

A charge-based model is presented for long-channel cylindrical surrounding-gate (SRG) MOSFETs from an intrinsic channel to a heavily doped body. The model derivation is based on an accurate inversion charge solution of Poissons equation in a cylindrical coordinate system. The general drain-current equation is obtained from Pao-Sahs dual integral, which is expressed as a function of inversion charge at the source and drain terminals. The model is valid for all regions of operation without employing any smoothing function. The model has been extensively verified by numerical simulations with a wide range of SRG MOSFET geometry parameters and channel doping concentrations, including the undoped channel.

Universal NBTI Compact Model for Circuit Aging Simulation under Any Stress Conditions

In this paper, a compact model for the negative bias temperature instability (NBTI) is developed by considering the interface-state generation and the hole-trapping mechanisms. This model shows accurate reproduction of the threshold voltage (Vth) degradations measured from samples fabricated with different dielectric materials as well as processes. A total of eight model parameters are introduced for describing the different degradation origins. The parameter values are verified to exhibit universal properties as a function of the electrical field within the gate oxide (Eox). By implementing the universal NBTI model into the compact model HiSIM, the dynamic NBTI effect and circuit performance degradation can be predicted.

Compact reliability model for degradation of advanced p-MOSFETs due to NBTI and hot-carrier effects in the circuit simulation

A compact reliability model is reported, which includes both the channel hot carrier (CHC) and the negative bias thermal instability (NBTI) effects in p-MOSFETs. The developed compact NBTI model, which describes both interface-state generation and hole-trapping mechanisms, is further improved by considering additionally the impact of the drain bias Vds. With increased Vds, the NBTI effect is weakened due to the reduction of the vertical gate oxide field, and the CHC effect is enhanced by the increased lateral channel electric field. Therefore, the threshold voltage is observed to decrease in the low Vds regime, and then increases again in the high Vds regime. Such “turn-around” characteristic is correctly modeled using the improved compact NBTI model. Implementation of this reliability model into the surface-potential-based compact model HiSIM enables accurate prediction of the CHC enhanced NBTI degradation for wide ranges of time duration and bias conditions. This allows real-time simulation for the circuit-performance degradation occurring during actual circuit operation.

A unified FinFET reliability model including high K gate stack dynamic threshold voltage, hot carrier injection, and negative bias temperature instability

A unified FinFET reliability model including high K stack dynamic threshold (HKSDT), hot carrier injection (HCI), and negative bias temperature instability (NBTI) has been developed and verified by experimental data. The FinFET-based circuit performances are simulated and compared under these reliability issues by HSPICE simulator after the inclusion of the presented model.

A physical based model to predict performance degradation of FinFET accounting for interface state distribution effect due to hot carrier injection

Abstract A physical based model for predicting the performance degradation of the FinFET is developed accounting for the interface state distribution effect due to hot carrier injection (HCI). The non-uniform distribution of interface state along the FinFET channel is first extracted by a forward gated-diode method and then reproduced by an empirical model. From this, a physical-based device model, which accounts for the interface state distribution effect, is developed to predict the performance degradation of FinFET. The result shows that the developed model not only matches well with the experimental data of FinFET in all operation regions, but also predicts the asymmetric degradation of saturation drain current in forward and reverse operation mode. Finally, the impact of HCI to a 6-T SRAM cell is simulated using HSPICE.

FinFET: From compact modeling to circuit performance

FinFET device, the promise one of all candidates which may extend CMOS scaling to 10nm and beyond, has attracted intensive research interest in recent years. In paralleling the process technology and circuit design methodology, a compact model which serves as a link between the process technology and circuit design is strongly demanded. In this paper, we first review the FinFET process technology including SOI-FinFET and bulk-FinFET. Then a potential-based compact model is proposed to describe the electrical characteristics of the FinFET transistor. The model is verified by 2-D numerical simulation and is implemented into HSPICE simulator. Finally, the reliability issue of the FinFET device and circuit functions are illustrated and analyzed, which are important for the practical applications and circuit design.

FinFET reliability study by forward gated-diode generation-recombination current

Reliability of FinFETs is studied in this paper using the forward gated-diode generation–recombination (G–R) current. The current–voltage characteristics of a FinFET are measured for parameter extraction and a mathematical algorithm is used to extract the stress-induced interface states and oxide traps of the FinFET from the G–R current measurement. It is observed that the stress-induced interface states and oxide traps can be distinguished by observing the shift of the peak G–R current in the body current (Ib) versus gate voltage (Vg) characteristic. The interface states cause a change in the maximum G–R current (ΔIpeak) while the oxide traps result in a shift of the gate voltage (ΔVg) corresponding to the ΔIpeak. Unlike bulk MOSFETs, the dominant degradation mechanism of FinFETs is found to be the oxide traps formation rather than the interface states generation.

Universal properties and compact modeling of dynamic hot-electron degradation in n-MOSFETs

A compact model for the n-MOSFET degradation is developed based on the trap-density increase, which is extracted from the measured 1/f noise characteristics. The trap density is explicitly included in the Poisson equation, which is solved within the framework of HiSIM. The measured real-time dynamic degradation of the I-V characteristics is successfully reproduced with this compact modeling approach. A further important advantage of the developed compact degradation model is the negligible cost in additional circuit-simulation time.

Gate Underlap Design for Short Channel Effects Control in Cylindrical Gate-all-around MOSFETs based on an Analytical Model

Abstract Gate underlap structure can be utilized to improve the immunity to short channel effects in MOSFET devices. In this work, gate underlap design scheme in cylindrical gate-all-around MOSFETs is explored based on an analytical model. This model takes into account the fringing field from gate electrode to underlap regions based on conformal mapping and a channel length transformation method. By solving Poisson equations in the underlap and channel regions and matching the boundary conditions, this model reproduces the channel potential profile in subthreshold operation region. Both symmetric and asymmetric underlap structures are covered. The developed model is verified extensively with TCAD simulations. A gate underlap design scheme is then provided based on this analytical model.