Cheol-Hong Kim

A Hybrid Technique for Medical Image Segmentation

Medical image segmentation is an essential and challenging aspect in computer-aided diagnosis and also in pattern recognition research. This paper proposes a hybrid method for magnetic resonance (MR) image segmentation. We first remove impulsive noise inherent in MR images by utilizing a vector median filter. Subsequently, Otsu thresholding is used as an initial coarse segmentation method that finds the homogeneous regions of the input image. Finally, an enhanced suppressed fuzzy c-means is used to partition brain MR images into multiple segments, which employs an optimal suppression factor for the perfect clustering in the given data set. To evaluate the robustness of the proposed approach in noisy environment, we add different types of noise and different amount of noise to T1-weighted brain MR images. Experimental results show that the proposed algorithm outperforms other FCM based algorithms in terms of segmentation accuracy for both noise-free and noise-inserted MR images.

A Hybrid Feature Model and Deep-Learning-Based Bearing Fault Diagnosis

Bearing fault diagnosis is imperative for the maintenance, reliability, and durability of rotary machines. It can reduce economical losses by eliminating unexpected downtime in industry due to failure of rotary machines. Though widely investigated in the past couple of decades, continued advancement is still desirable to improve upon existing fault diagnosis techniques. Vibration acceleration signals collected from machine bearings exhibit nonstationary behavior due to variable working conditions and multiple fault severities. In the current work, a two-layered bearing fault diagnosis scheme is proposed for the identification of fault pattern and crack size for a given fault type. A hybrid feature pool is used in combination with sparse stacked autoencoder (SAE)-based deep neural networks (DNNs) to perform effective diagnosis of bearing faults of multiple severities. The hybrid feature pool can extract more discriminating information from the raw vibration signals, to overcome the nonstationary behavior of the signals caused by multiple crack sizes. More discriminating information helps the subsequent classifier to effectively classify data into the respective classes. The results indicate that the proposed scheme provides satisfactory performance in diagnosing bearing defects of multiple severities. Moreover, the results also demonstrate that the proposed model outperforms other state-of-the-art algorithms, i.e., support vector machines (SVMs) and backpropagation neural networks (BPNNs).

A GPU-based (8, 4) Hamming decoder for secure transmission of watermarked medical images

Medical image watermarking has received increasing attention as wide security services in the e-diagnosis system, where the images are transmitted through the internet among the patient, primary physicians, and referred physicians. These images are highly prone to become corrupted and erroneous due to the inherent noise in the wireless medium. Such error results in serious adverse impacts including inconsistent and unreliable transmission, faulty watermark detection, and faulty diagnosis. To solve the problem, we propose a (8, 4) Hamming code based error correction. In addition, we implement the Hamming code on a graphics processing unit (GPU) to accelerate and meet the real-time requirement. The experimental results demonstrate that the GPU based approach exceedingly outperforms the CPU based error correction in terms of execution time.

Accelerating a Bellman–Ford Routing Algorithm Using GPU

This paper presents a graphics processing unit (GPU)-based implementation of the Bellman–Ford (BF) routing algorithm used in distance-vector routing protocols. In the proposed GPU-based approach, multiple threads concurrently run in numerous streaming processors in the GPU to update the routing information instead of computing the individual vertex distances one-by-one, where an individual vertex distance is considered as a single thread. This paper compares the performance and energy consumption of the GPU-based approach with those of the equivalent central processing unit (CPU) implementation for varying the number of vertices. Experiment results show that the proposed approach outperforms the equivalent sequential CPU implementation in terms of execution time by exploiting massive parallelism inherent in the BF routing algorithm.

Parallel implementation of the FFT algorithm using a multi-core processor

Fast Fourier Transform (FFT) is an upgraded version of discrete Fourier Transform (DFT) which reduces the number of computations. However, FFT demands tremendous computational and I/O requirements. To solve this problem, this paper proposes a multi-core architecture which consists of eight processing elements to enhance the performance of FFT. Experiment results indicate that the proposed approach outperforms commercial TMS320C6416 DSP in terms of performance and energy efficiency. These results show that our proposed architecture is a suitable candidate to enhance the performance of FFT.

A high-performance, resource-efficient, reconfigurable parallel-pipelined FFT processor for FPGA platforms

Abstract The fast Fourier transform (FFT) algorithm is widely used in digital signal processing systems (DSPs); hence, the development of a high-performance and resource-efficient FFT processor that conforms to the processing and precision requirements of real-time signal processing is highly desirable. We propose an FFT processor for field programmable gate array (FPGA) devices, based on the radix-2-decimation-in-frequency (R2DIF) algorithm. An appropriately modified parallel double-path delay commutator (DDC) architecture for radix-2 with continuous dual-input and dual-output streams (CoDIDOS) is proposed to increase throughput and reduce latency in FFT computation. The chip-area of the proposed design is reduced by decreasing the memory footprint of the complex twiddle factor multipliers. A multiplication scheme based on a combination of the unrolled coordinate rotation digital computer (CORDIC) and the canonical signed digit-based binary expression (CSDBE) is used to multiply the complex twiddle factors without requiring memory blocks for their storage. The CSDBE technique is proposed to optimize the multiplication of constants in the architecture. The proposed FFT processor is implemented as an intellectual property (IP) core and tested on a Xilinx Virtex-7 FPGA. Experimental results confirm that the proposed design improves the speed, latency, throughput, accuracy, and resource utilization of computation on FPGA devices over existing designs.

Baleen Whale Sound Synthesis using a Modified Spectral Modeling

Spectral modeling synthesis (SMS) has been used as a powerful tool for musical sound modeling. This technique considers a sound as a combination of a deterministic plus a stochastic component. The deterministic component is represented by the series of sinusoids that are described by amplitude, frequency, and phase functions and the stochastic component is represented by a series of magnitude spectrum envelopes that functions as a time varying filter excited by white noise. These representations make it possible for a synthesized sound to attain all the perceptual characteristics of the original sound. However, sometimes considerable phase variations occur in the deterministic component by using the conventional SMS for the complex sound such as whale sounds when the partial frequencies in successive frames differ. This is because it utilizes the calculated phase to synthesize deterministic component of the sound. As a result, it does not provide a good spectrum matching between original and synthesized spectrum in higher frequency region. To overcome this problem, we propose a modified SMS that provides good spectrum matching of original and synthesized sound by calculating complex residual spectrum in frequency domain and utilizing original phase information to synthesize the deterministic component of the sound. Analysis and simulation results for synthesizing whale sounds suggest that the proposed method is comparable to the conventional SMS in both time and frequency domain. However, the proposed method outperforms the SMS in better spectrum matching.

An Efficient Pipelined Feedback Processor for Computing a 1024-Point FFT Using Distributed Logic

This paper proposes an effective fast Fourier transform (FFT) processor for 1024-point computation based on the radix-2 of decimation-in-frequency (R2DIF) and uses the pipelined feedback (PF) technique via shift registers to efficiently share the same storage between the inputs and outputs during computation. The large memory footprint of the complex twiddle factor multipliers, and hence, area on a chip, of the proposed design is reduced by employing the coordinate rotation digital computer (CoRDiC), which replaces the complex multipliers and does not require memory blocks to store the twiddle factors. To enhance the efficient usage of the hardware resources, the proposed design only uses distributed logic. This can eliminate the use of dedicated functional blocks, which are usually limited to the target chip. The entire proposed system is mapped on a Virtex-7 field-programmable gate array (FPGA) for functional verification and synthesis. The achieved result is the proposed FFT processor more effective in terms of the speed, precision, and resource, as shown in experimental results.

Accelerating Envelope Analysis-Based Fault Diagnosis Using a General-Purpose Graphics Processing Unit

Reliable fault diagnosis in the bearings of an induction motor is of paramount importance for preventing unscheduled motor breakdowns and significant economic losses. This paper presents a fault diagnosis approach using a genetic algorithm and time-varying multi-resolution envelope analysis to select an optimal passband and the most discriminative fault components, respectively, in the acoustic emission signal from bearings. However, the computational complexity of the approach limits its use in real-time applications. To address that issue, this paper presents a general-purpose graphics processing unit (GPGPU)-based fault diagnosis methodology to accelerate the process via the optimal use of the GPGPU’s global and shared memory resources and parallel computing abilities. Experimental results show that the proposed GPGPU implementation is approximately 19 times faster and uses 570 % less energy than CPU implementation.

Real-time Night Visibility Enhancement Algorithm Using the Similarity of Inverted Night Image and Fog Image

In this paper, we propose improved night visibility enhancement algorithm based on haze removal method. The proposed method use new haze removal method in place of the conventional method. This de-haze method is very good and faster than traditional method. It also uses a further Contrast Limit Adaptive Histogram Equalization (CLAHE) for sharpening the image. The proposed method can be applied to any application that uses a visible light camera, and it is appropriate to apply a black box, vehicle camera, and cell phone camera, since it is possible that real-time processing.