Cheong-Ghil Kim

An efficient method to create business level events using complex event processing based on RFID standards

RFID systems should be designed to process a large number of RFID data in real time. Therefore, there have been much research and company studies regarding RFID data processing. One of methods is CEP (Complex Event Processing), which can provide a method to process RFID data efficiently. However, previous work is just focused on raw RFID data processing, such as data filtering, the elimination of duplicated data, and the aggregation of data. Also, it creates primitive events based on just one physical or logical reader. Therefore, processing overhead for complex events may increase. And it cannot provide business level events. Therefore, we propose a method that can reduce processing overhead and create business level events by using CEP. Proposed method provides two primitive events that are defined by using the relationship of two readers. Thus, when any pattern of events is matched for a specific complex event, business level events can be generated and execution time can be reduced comparing with other mechanisms without those events. And, execution time can be reduced by about 57% as compared to others.

A Selective Ahead-Of-Time Compiler on Android Device

The runtime environment of Android is based on its own Java Virtual Machine(JVM) called Dalvik Virtual Machine (DVM) which is said to be having overhead of interpreting every bytecode to machine code during runtime just like other JVMs. There are already well known techniques to overcome runtime overhead of interpreting and Google has adapted one of them which is Just-In-Time Compiler (JITC) since Android 2.2, Froyo. Google chose trace based JITC to JIT compile only the hottest of hot code by using lazy fashion with counting strategy to minimize memory usage, thus applying various optimization techniques during JIT compilation to generate more efficient machine code is limited. In order to minimize runtime interpreting and compiling overhead, here a selective Ahead-Of-Time Compiler (AOTC) which generates machine code at static compile time with abundant optimization techniques for the selected hot methods by profiling will be introduced. The experimented results show that AOT compiling hot methods at static compile time and letting the others to aim the benefit of runtime JITC gives 5% of performance upgrade in average on ARM11 600MHz target environment.

An FPGA implementation of whitted-style ray tracing accelerator

This paper presents an FPGA implementation of a full whitted-style ray tracing accelerator. It achieves about 1.3 M rays per second over realistic 3 D scenes. The future implementation with ASIC is expected to achieve real-time performance.

A Parallel Approach to Mobile Web Browsing

This paper present a parallel approach about mobile web browsing, especially layout and paint parts. Web browser is one of the most frequently used applications in mobile devices and performance of web browser is an important factor affecting mobile device user experience. From our previous research, we found that layout and paint takes significant portion of web browser execution time and has similar execution characteristics. In this paper, we propose parallel render tree traversal algorithm for layout and paint parts in web browser: creating thread for sub-tree traversal processing. Moreover, to validate proposed Algorithm, we design a simple simulation implementing parallel tree traversal with web page render tree. The experiment results show that execution time is reduced average 28% in dual-core, 32% in quad-core compare to single-thread execution in paint simulation. In layout simulation, average 38% in dual-core, 57% in quad-core execution time is reduced.

A pipelined hardware architecture for motion estimation of H.264/AVC

The variable block size motion estimation (VBSME) presented in the video coding standard H.264/AVC significantly improves coding efficiency, but it requires much more considerable computational complexity than motion estimation using fixed macroblocks. To solve this problem, this paper proposes a pipelined hardware architecture for full-search VBSME aiming for high performance, simple structure, and small controls. Our architecture consists of 1-D arrays with 64 processing elements, an adder tree to produce motion vectors (MVs) for variable block sizes, and comparators to determine the minimum of MVs. This can produce all 41 MVs for variable blocks of one macroblock in the same clock cycles to other conventional 1-D arrays of 64 PEs. In addition, this can be easily controlled by a 2-bit counter. Implementation results show that our architecture can estimate MVs in CIF video sequence at a rate of 106 frames/s for the 32×32 search range.

Implementation of a Low Cost Home Energy Saver Based on OpenWrt

This paper introduces a system that can effectively save home energy by applying a small embedded system through remote control. We used a wireless router based on OpenWrt for the platform to develop an embedded system and a smart phone for the remote LED light control. The system was implemented by connecting a wireless router with an OS of OpenWrt installed and an interface board with an LED attached. The smart phone, which was the remote control device, was implemented by TCP/IP programming. The operation of the remote control system was verified by socket communication between the smart phone and the wireless router, and by USB communication between the wireless router and the interface board.

The Stack Allocation Technique on Android OS

Garbage collection is one of major reason for performance degradation on Android OS. Escape analysis can be one of techniques to prevent performance degradation and Google has tried to implement scalar replacement through the escape analysis. But it does not become Android default functionality. This paper took it and compared with our proposed stack allocation method. The experimental result shows scalar replacement has no effect at all but stack allocation produce effective results. The CaffeinMark benchmark also shows no performance degradation in spite of additional instructions.

2-D discrete cosine transform (DCT) on meshes with hierarchical control modes

An effective matrix operation is critical to process 2-D DCT. This paper presents a hierarchically controlled SIMD array (HCSA) well suited to matrix computations, in which a conventional 2-D torus is enhanced with the hierarchical organization of control units and the global data buses running across the rows and columns. The distinguished features of the HCSA are the diagonally indexed concurrent broadcast and the efficient data exchanges among PEs through either row or column broadcast. Therefore, the HCSA can provide significant improvement on computation steps of DCT. For the performance evaluation, an algorithmic mapping method is used and the number of computation steps is analytically compared with semisystolic architecture.

An Adaptive LOD Setting Methodology with OpenGL ES Library on Mobile Devices

This paper presents an adaptive LOD (level-of-detail) configuration method for 3D (three dimensions) applications and games via OpenGL ES API level in mobile computing devices. The proposed method is designed by using many interesting properties. The adaptive LOD configuration methodology can automatically trade-off between quality and performance and achieve an acceptable result by adjusting these LOD setting options. This paper describes basic structure showing how to execute by parameter modification of OpenGL ES API and shader reduction of OpenGL ES API. By using the proposed method, the performance of mobile GPU can be significantly improved by automatic scheduling method balancing trade-offs between visual quality and performance to improve UX (user experience). Specifically, users can simply turn on the switch to apply the proposed method for best effectiveness, and also any other action is not required because these methodologies do not rely on source code. Experimental result by using benchmarks shows that the proposed technique allows around 24 percent performance improvement for all applied methodologies, and around 4 percent improvement for some selected methodologies in exchange for about 14 percent and 2 percent decreases in quality, respectively. And the result in fluid simulation shows that the proposed technique can provide 82 percent speedup.

Non-Volatile Unified Memory Page Management for Improving Performance

Newly emerging non-volatile memorys future is promising and challenging because its performance and power consumption has been improved significantly. The performance improvement triggers these to be a major part of the todays generation computer systems in replacing main memory specially. This research particularly focuses on the page fault and page swap management via Operating System (OS) in order to improve the performance by employing unified memory system (UMS). This proposes, merging of conventional main memory and storage into a single memory layer, called as Unified Memory System. Also the proposed module is designed virtually in two zones, static zone and dynamic zone to support conventional memory management. For this, we analyze the operating system memory management behavior and its tendency to manage the non-volatile UMS through OS kernel for improving system performance. Avoiding data duplication between main memory and storage and frequent page faults are the major concern of this research, unlike a conventional DRAM main memory based system. We utilize phase change memory (PCM) as a suitable candidate for constructing UMS, because of its high density and non-volatility features. We depict the significant number of reduced page faults and execution improvement which will support the fast booting of the systems in near future.