Chester M. Nibby | Researchain

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Archive | 1982

Remap method and apparatus for a memory system which uses partially good memory devices

Chester M. Nibby; Reeni Goldin; Timothy A. Andrews

Archive | 1980

Sequential chip select decode apparatus and method

Robert B. Johnson; Chester M. Nibby; Dana W. Moore

Archive | 1982

Memory system with automatic memory configuration

Robert B. Johnson; Chester M. Nibby; Edward R. Salas

Archive | 1981

Identification apparatus for use in a controller to facilitate the diagnosis of faults

Robert B. Johnson; Chester M. Nibby; Edward R. Salas

Archive | 1997

Adaptively generating timing signals for access to various memory devices based on stored profiles

James F. Bertone; Bruno DiPlacido; Thomas F. Joyce; Martin Massucci; Lance J. McNally; Thomas L. Murray; Chester M. Nibby; Michelle A. Pence; Marc Sanfacon; Jian-Kuo Shen; Jeffrey S. Somers; G. Lewis Steiner; William S. Wu; Norman J. Rasmussen; Suresh K. Marisetty; Puthiya K. Nizar

Archive | 1991

High speed burst read address generation with high speed transfer

Raymond D. Bowden; Chester M. Nibby

Archive | 1980

Memory controller with queue control apparatus

Robert B. Johnson; Chester M. Nibby

Archive | 1983

Memory identification apparatus and method

Edward R. Salas; Edwin P. Fisher; Robert B. Johnson; Chester M. Nibby; Daniel A. Boudreau

Archive | 1979

Memory present apparatus

William Panepinto; Chester M. Nibby

Archive | 1987

Cache resiliency in processing a variety of address faults

George J. Barlow; James W. Keeley; Chester M. Nibby

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