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Dive into the research topics where Chetan Verma is active.

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Featured researches published by Chetan Verma.


electronics packaging technology conference | 2015

Faraday cage for EMC improvement of electronic devices

Shailesh Kumar; Rishi Bhooshan; Sumit Varshney; Chetan Verma; Lye Gideon

In conventional packaging there is a considerable scope of noise coupling with external environment. This may cause the device in concern to fail due to EMI and may also cause other electronic device in the vicinity to fail due the electro-magnetic radiations from the device in concern. In order to reduce the coupling between two high frequency signals, providing a ground shield between them is a common practice - both inside the die as well as on the BGA packages. In Lead frame packages, the technique is though limited to extremely small pin packages (6-10 pins) wherein a portion of the flag metal is cut in such a way so as to provide a ground shield between the pins. This technique fails for medium or high pin packages. The only other option is to connect every alternate lead_to ground to reduce coupling noise between the package pins. This reduces the effective number of usable pins and is not desirable. Resultantly, the lead frame packages suffer from low noise immunity for highly sensitive signals, leading to functional failures.


electronics packaging technology conference | 2014

BGA packaging using insulated wire for die area reduction

Shailesh Kumar; Vikas Garg; Chetan Verma; Rishi Bhooshan; Poh Zi-Song; L.C. Tan

In conventional wire bonded packages, design rules require that individual bond wires not touch each other. Also, handling of bonded units may cause wire disturbance leading to wire short. Insulated wire bonding techniques eliminate this requirement by coating a non conductive layer over the bond wires as shown in Fig.1 and thus, electrical isolation is maintained even after wires physically touch each other [1-2]. The focus of this paper is to leverage the insulated wire-bonding technology for die design implementation efficiency in terms of improving electrical parameters and die size reduction. Two specific implementation are discussed in this paper. One is to implement off-chip decoupling capacitor and use it to replace on-die capacitors required for signal integrity and save precious silicon area. Second implementation is about realizing mesh type power grid to improve the IR drop and simultaneously get rid of multiple Power/Ground pads and thus, save silicon area.


Archive | 2013

Timing path slack monitoring system

Chetan Verma; Amit Kumar Dey; Amit Roy; Vijay Tayal


Archive | 2012

MEMORY DEVICE REDUNDANCY MANAGEMENT SYSTEM

Chetan Verma; Piyush Kumar Mishra; Ashish Sharma


Archive | 2010

Clock buffer circuit

Chetan Verma; Nitin Verma


Archive | 2010

BOND PAD FOR SEMICONDUCTOR DIE

Chetan Verma; Shailesh Kumar; Meng Kong Lye


Archive | 2014

SEMICONDUCTOR DEVICE WITH PACKAGE-LEVEL DECOUPLING CAPACITORS FORMED WITH BOND WIRES

Chetan Verma; Rishi Bhooshan; Vikas Garg; Shailesh Kumar; Navas Khan Oratti Kalandar


Archive | 2013

MOS transistor with forward bulk-biasing circuit

Amit Roy; Amit Kumar Dey; Kulbhushan Misri; Vijay Tayal; Chetan Verma


Archive | 2011

Method for reducing surface area of pad limited semiconductor die layout

Chetan Verma; Sumeet Aggarwal; Meng Kong Lye


Archive | 2006

INTEGRATED CIRCUIT CHIP WITH CONNECTIVITY PARTITIONING

Chetan Verma; Rohit Gupta; Piyush Kumar Mishra

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Vijay Tayal

Freescale Semiconductor

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Amit Roy

Freescale Semiconductor

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Vikas Garg

Freescale Semiconductor

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