Chi-Mao Hsu

A comprehensive process engineering on TDDB for direct polishing ultra-low k dielectric Cu interconnects at 40nm technology node and beyond

The failure ratios of the three typical time-dependent dielectric breakdown (TDDB) failure modes, including top interface, sidewall and bottom corner areas, have been identified for a direct polishing ultra low k (ULK) dielectric Cu back-end-of-line (BEOL) structure at 40nm node. The Cu surface roughness of the metal lines, and the adhesion and thickness of the metal capping layers are strongly correlated to the top interface failure mode. The dielectric constant of the ULK and the concentration of the aluminum-doped Cu (CuAl) seed layer could be related to the sidewall failure mode. The bottom corner failures are induced by inappropriate Cu barrier re-sputter processes. In this study, the TDDB reliability performance can be effectively improved by evaluating a post-Cu chemical mechanical polishing (Cu CMP) cleaning process with smooth Cu surface roughness, developing a better step coverage with multi-layer capping layer, using a slightly higher dielectric constant ULK film, replacing a conventional pure Cu with a CuAl seed layer and optimizing the Cu barrier layer deposition process. The lifetime of the TDDB can be significantly improved over three orders (larger than 10000 years) as implementing an optimized integrated Cu with ULK BEOL structures at 40nm technology node.

Investigation pre-amorphization implantation on nickel silicide formation

Pre-amorphization implantation (PAI) of various energy and dosage are used on Ni-Silicide formation, which has achieved amorphism-like NiSi films. The electric characteristic, physical morphology and metallurgical of the NiSi were identified by sheet resistance, grazing incident X-ray diffraction (GIXRD), and selected-area electron diffraction (SAD) analysis. Result shows that lower energy and higher dosage of ion implantation can get amorphism-like NiSi film.

A novel pre-clean process of BEOL barrier-seed process to enhance reliability performance of advanced 40nm node

With scaling down of device geometry and keeping improvement of the chip resistance capacitance (RC) delay, it is necessary to reduce k value. A porous ultra low k-value (ULK) dielectric film is integrated into Cu interconnects of advanced 40 nm. There are several papers discussing about the interface effect between ULK film and barrier on reliability performance [1][2]. This paper will discuss the effect of pre-clean process on reliability performance before barrier and Cu-seed layer deposition that will strong affect the interface properties. Also, the early failure mode of each pre-clean process will be discussed as well to clarify the proposed mechanism.