Chiaki Takano

Improving collector-current uniformity in emitter-graded AlGaAs/GaAs heterojunction bipolar transistors

To investigate the effect of a graded layer on collector-current uniformity, two types of HBTs were fabricated by metalorganic chemical vapor deposition (MOCVD). One type had a bandgap graded layer at the emitter-based interface to eliminate the conduction-band spike. The other type was a conventional HBT (heterojunction bipolar transistor) with an abrupt heterojunction fluctuated due to the fluctuation of the barrier energy from the emitter to the base. The bandgap-graded layer drastically suppressed the fluctuation of the collector current. the standard deviation of the threshold voltage was improved from 3.03 to 0.42 V by adopting bandgap grading at the emitter-based interface.<<ETX>>

Emitter grading in AlGaAs/GaAs heterojunction bipolar transistor grown by metalorganic chemical vapor deposition

The effect of emitter grading on the injection barrier of Al0.3Ga0.7As/GaAs heterojunction bipolar transistor grown by metalorganic chemical vapor deposition was studied. The barrier height for electrons injected from the emitter was determined from the temperature dependence of collector current. It has been directly confirmed that the barriers for graded heterojunction and GaAs homojunction are comparable. However, the grading enhanced the recombination at the emitter‐base depletion region, which suggests that the hole confinement was reduced.

Monolithic integration of 5-Gb/s optical receiver block for short distance communication

The authors developed an optical receiver block for applications such as board-to-board or chip-to-chip data communications. They implemented the optical receiver block with an interdigit metal-semiconductor-metal (MSM)type photodetector and 0.35- mu m gate junction FETs which were monolithically integrated on a GaAs substrate. High-speed operation of 5 Gb/s was observed with a relatively low power consumption of 8.2 mW. >

Low-power performance of 0.5- mu m JFET for low-cost MMIC's in personal communications

The low-power microwave performance of an enhancement-mode ion-implanted GaAs JFET is reported. A 0.5- mu m*100- mu m E-JFET with a threshold voltage of V/sub th/=0.3 V achieved a maximum DC transconductance of g/sub m/=489 mS/mm at V/sub ds/=1.5 V and I/sub ds/=18 mA. Operating at 0.5 mW of power with V/sub ds/=0.5 V and I/sub ds/=1 mA, the best device on a 3-in wafer achieved a noise figure of 0.8 dB with an associated gain of 9.6 dB measured at 4 GHz. Across a 3-in wafer the average noise figure was F/sub min/=1.2 dB and the average associated gain was G/sub a/=9.8 dB for 15 devices measured. These results demonstrate that the E-JFET is an excellent choice for low-power personal communication applications.<<ETX>>

10 K gate GaAs JFET sea of gates

The first GaAs 10 K-gate sea of gates has been successfully fabricated using junction FETs (JFETs) with a gate length of 0.5 mu m. A basic cell is designed to comprise both a direct coupled FET logic (DCFL) four-NOR circuit and a source coupled FET logic (SCFL) inverter circuit with an identical enhancement-type JFET. Each input and output level is designed to be compatible with Si emitter-coupled-logic (ECL), CMOS, and transistor-transistor-logic (TTL) levels. Unloaded and loaded DCFL gate delays are 21 and 180 ps/gate with power consumption of 0.4 and 0.5 mW/gate, respectively. The toggle frequency of the T-type flip-flop is 3.9 and 4.4 GHz for DCFL and SCFL, respectively. >

High-speed DCFL circuits with very shallow junction GaAs JFETs

High-speed DCFL (direct-coupled FET logic) circuits implemented with advanced GaAs enhancement-mode J-FETs are discussed. A divide-by-four static frequency divider operates at up to 6 GHz with a power consumption of 20 mW/flip-flop. A high channel concentration of more than 1*10/sup 18/ cm/sup -3/ together with a very shallow junction depth of less than 30 nm for the p/sup +/-gate results in a transconductance as high as 340 mS/mm at a gate length of 0.8 mu m. Open-tube diffusion of Zn using diethylzinc and arsine makes it possible to control a very shallow p/sup +/-layer less than 10 nm thick. The propagation delay time, as measured with a ring oscillator, was 22 ps/gate with a power consumption of 0.42 mW/gate. >

Band offset effect on transport in Al x Ga 1-x As/GaAs heterojunction bipolar transistors grown by metalorganic chemical vapor deposition

AlxGa1-xAs/GaAs heterojunction bipolar transistors were grown with x in the emitter from 0 to 0.57 and the band offset effect on electron transport has been studied using a new technique. The data, though preliminary, indicate that the transport is dominated by electrons near the conduction-band minima when x < 0.45, but not when x = 0.57.

Temperature stability of ultrahigh-speed GaAs JFET ICs

Ultrahigh-speed digital integrated circuits (ICs) implemented with GaAs/int JFETs are confirmed to be reliable in a wide variety of temperatures. Divide-by-256/258 dual-modulus prescaler ICs using source-coupled FET logic (SCFL) circuits that can operate up to 9 GHz have temperature coefficients of operating frequency stability and input power sensitivity of -17.2 MHz/degree and +0.12 dBm/degree between -20 and +100 degrees C, respectively. Direct-coupled FET logic (DCFL) circuits were also confirmed to have very small temperature coefficients. The variations of the maximum operating frequency and the input power sensitivity of the DCFL divide-by-4 divider IC are -1.93 MHz/degree and +0.47 dBm/degree, respectively, between -60 and +100 degrees C. The variation in the threshold voltage of the JFET is -0.88 mV/degree which is very small for the temperature stability of GaAs digital ICs. >