Chien Hung Tsai

A Fast-Transient Quasi-V

A switching regulator with quasi-V2 adaptive on-time (AOT) control that provides a fast load transient response is proposed in this paper. The feed-forward path network allows the proposed switching regulator to achieve a fast transient response and stable operation without requiring an output capacitor with large equivalent series resistance. The proposed adaptive on-time controller makes the switching frequency pseudofixed in the continuous conduction mode and works in the pulse-frequency modulation mode under ultralight-load conditions to maintain the conversion efficiency. The AOT controller adjusts the on-time according to the supply voltage and load current conditions. The measurement results verify that the switching regulator can operate under load current between 5 and 800 mA for the supply voltage of 3.3-4.2 V and an output voltage of 1.2 V. The recovery time is 3.6 μs and the voltage drop is 75 mV when the load current is increased from 5 to 750 mA.

^{\bf 2}

A low-dropout (LDO) regulator with tail current control (TCC) is presented. The TCC consists of a dual differential pair, a 5-bit current digital-to-analog converter, and a current summation circuit. The TCC adjusts the tail current ratio of the dual differential pair of the LDO regulator to achieve a programmable output voltage using 5-bit digital signals. A supply-ripple isolation mechanism is added to improve the power supply rejection over a wide frequency range. The proposed design is fabricated in the TSMC 0.18-μm 1-poly 6-metal complementary metal-oxide-semiconductor process. Experimental results show that the LDO regulator has a 32-level programmable output voltage ranging from 1 to 1.2 V, making the LDO regulator suitable for correcting the oscillator frequency of a digital pulsewidth modulator.

Switching Buck Regulator Using AOT Control With a Load Current Correction (LCC) Technique

This paper presents a multimode digital controller with dead-time self-exploration (DTSE) for synchronous buck converters that simultaneously achieves high efficiency and a fast transient response. The automatic mode switching technique uses the duty-cycle command to determine multimode operation without sensing any current signals. The DTSE algorithm is used to minimize the steady-state duty-cycle command to maximize the converter efficiency. During load transients, a nonlinear control mode is employed to reduce the transient response. The proposed digital controller is fabricated in a CMOS 0.18-μm process. The experimental results for a 1.2-V output voltage show that the measured power efficiency is higher than 85% for a load range of 10-600 mA and that the measured transient response is improved by 28% compared to that of the traditional voltage-mode converter.

A Low-Dropout Regulator With Tail Current Control for DPWM Clock Correction

For battery-powered electronic products, one way to extend battery life is to use a versatile step-up/step-down DC-DC converter. A new versatile step-up/step-down switched-capacitor-based converter structure is proposed, and its efficiency is analyzed. In the step-down case, the efficiency is the same as, or even better than the efficiency of linear regulators.

Digitally Controlled Switching Converter With Automatic Multimode Switching

The propagation delay of a comparator and dead time causes the duty-discontinuity region near the boundary of the step-down and step-up regions in a non-inverting buck-boost (NIBB) converter. The duty-discontinuity region leads to an unstable output voltage and an unpredictable output voltage ripple, which might cause the entire power system to shut down. In this paper, a mode-transition technique called duty-lock control is proposed for a digitally controlled NIBB converter. It locks the duty cycle and eliminates the error between the output voltage and the reference signal by using a proposed fixed reference scheme that ensures the stability of the digital controller and output voltage. The experimental results that were applied to a field-programmable gate array-based platform revealed that the output voltage of the NIBB converter is stable throughout the entire transition region, without any efficiency tradeoffs. The input voltage of the converter that was provided by a Li-ion battery was 2.7-4.2 V, and the output voltage was 1.0-3.6 V, which is suitable for radio-frequency power amplifiers. The switching frequency was 500 kHz, and the maximum load current was 450 mA.

A Versatile Step-Up/Step-Down Switched-Capacitor-Based DC-DC Converter

This paper describes the complete design and implementation of a low-power sigma-delta DPWM (Σ-Δ DPWM) controller for switching converter which can operate at a very high frequency. In the previous design approach, the effective resolution of Σ-Δ DPWM, i.e. the effective number of bit (ENOB) is over-estimated by using the conventional signal-to-noise ratio (SNR) with a continuous-time sine-wave input. Therefore, the modified expressions of SNR and ENOB are presented, which are suitable for the digital sigma-delta modulator (Σ-Δ MOD) with a discrete-time discrete-amplitude signal. In addition, the trade off between the hardware area consumption and the SNR value is discussed. Finally, the system simulation results of the general 10-b DPWM controller and 10-b effective resolution ΣΔ DPWM controller for buck converter are shown to verify the proposed design approach

A stable mode-transition technique for a digitally controlled non-inverting buck-boost DC-DC Converter

This paper presents a peak current-controlled (PCC) single-inductor dual-output (SIDO) DC-DC buck converter with a time-multiplexing (TM) scheme. Small signal modeling, system compensation, and circuit implementation are discussed. Simulation and measurements confirm the effectiveness of the proposed method. The converter was fabricated using TSMC 0.35-µm CMOS technology. The input supply voltage is from 2.7∼4.2V. Two outputs are specified at 2.5V/36mA and 1.8V/20mA, respectively, and operated at 500 KHz with a 1-µH inductor and 20-µF capacitors.

Design and implementation of sigma-delta DPWM controller for switching converter

This paper presents the use of a combined random pulse position modulation (RPPM)/digital pulsewidth modulation (DPWM) digital controller for a buck converter to simultaneously achieve low-conductive electromagnetic interference (EMI) and a fast transient response. An area-efficient RPPM/DPWM controller suitable for advanced system-on-chip integration is proposed and implemented in a field-programmable gate array-based prototype to verify its EMI-suppression capability. The experimental results for a 1.2-V digital buck converter show that the proposed digital switching regulator can switch between RPPM and DPWM modes smoothly and automatically. Closed-loop system measurements demonstrate that, compared to DPWM, up to 17.27 and 14.99 dB power spectra reductions are obtained in the input current and switching node, respectively.

A peak-current controlled single-inductor dual-output DC-DC buck converter with a time-multiplexing scheme

This paper presents a fully integrated single-inductor dual-output (SIDO) buck-boost or boost-boost DC-DC converter with power-distributive control. This converter works under voltage mode control to have better noise immunity, uses fewer power switches/external compensation components to reduce cost, and is thus suitable for system on chip (SoC) applications. The proposed SIDO converter was fabricated in TSMC 0.35μm 2P4M CMOS technology with input supply voltage 2.7–3.3 V. The first output VO1 can operates either at buck mode or boost mode (output voltage in between 2.5V to 5V), while the second output VO2 can only operates at boost mode (output voltage 3.6V).

A Digitally Controlled Switching Regulator With Reduced Conductive EMI Spectra

The design of a compact low-power highspeed class-AB buffer amplifier for driving the large column line loads of large-size TFT-LCD is presented in this paper. The class-AB buffer amplifier can drive large column line loads up to lOOOpF within 1.28 mus. The proposed class-AB buffer amplifier is implemented with a standard 0.35 mum CMOS 2-poly 4-metal process technology and simulated using HSPICE. The measurement results show that the power consumption of 25.67 muW, and exhibits the slew rates of 4.5V/ mus and 5V/ mus for rising and falling edges, respectively, under a lOOOpF load. The active area of this class-AB output buffer amplifier is only 47 x 45 mum2.