Chih-Hung Chou

Detection of the Third Heart Sound Based on Nonlinear Signal Decomposition and Time–Frequency Localization

This study presents a precise way to detect the third (S3) heart sound, which is recognized as an important indication of heart failure, based on nonlinear single decomposition and time- frequency localization. The detection of the S3 is obscured due to its significantly low energy and frequency. Even more, the detected S3 may be misunderstood as an abnormal second heart sound with a fixed split, which was not addressed in the literature. To detect such S3, the Hilbert vibration decomposition method is applied to decompose the heart sound into a certain number of subcomponents while intactly preserving the phase information. Thus, the time information of all of the decomposed components are unchanged, which further expedites the identification and localization of any module/section of a signal properly. Next, the proposed localization step is applied to the decomposed subcomponents by using smoothed pseudo Wigner-Ville distribution followed by the reassignment method. Finally, based on the positional information, the S3 is distinguished and confirmed by measuring time delays between the S2 and S3. In total, 82 sets of cardiac cycles collected from different databases including Texas Heart Institute database are examined for evaluation of the proposed method. The result analysis shows that the proposed method can detect the S3 correctly, even when the normalized temporal energy of S3 is larger than 0.16, and the frequency of those is larger than 34 Hz. In a performance analysis, the proposed method demonstrates that the accuracy rate of S3 detection is as high as 93.9%, which is significantly higher compared with the other methods. Such findings prove the robustness of the proposed idea for detecting substantially low-energized S3.

Memory-efficient buffering method and enhanced reference template for embedded automatic speech recognition system

This work realises a memory-efficient embedded automatic speech recognition (ASR) system on a resource-constrained platform. A buffering method called ultra-low queue-accumulator buffering is presented to efficiently use the constrained memory to extract the linear prediction cepstral coefficient (LPCC) feature in the embedded ASR system. The optimal order of the LPCC is evaluated to balance the recognition accuracy and the computational cost. In the decoding part, the proposed enhanced cross-words reference templates (CWRTs) method is incorporated into the template matching method to reach the speaker-independent characteristic of ASR tasks without the large memory burden of the conventional CWRTs method. The proposed techniques are implemented on a 16-bit microprocessor GPCE063A platform with a 49.152 MHz clock, using a sampling rate of 8 kHz. Experimental results demonstrate that recognition accuracy reaches 95.22% in a 30-sentence speaker-independent embedded ASR task, using only 0.75 kB RAM.

An automatic speaker-speech recognition system for friendly HMI based on binary halved clustering

This work presents a low-cost and fast-trainable automatic speaker-speech recognition (ASSR) system, by proposed binary halved clustering (BHC) method for human-machine interface (HMI) on an embedded platform, owing to the trait of low cost in ASSR system is essential and affordable for real-world application. In addition, fast-trainable ability can provide fast responding time. The reduction of waiting time makes the proposed HMI to be friendly for users. The speech recognition uses enhanced cross-word reference templates (ECWRTs) for template training type. The novel BHC method uses binary-halved splitting to generate speaker models for low complexity requirement. The regularity of binary halved behavior is beneficial for data scheduling and resource sharing in the embedded ASSR system. Compared with the conventional works, simulation results indicate that the proposed hardware accelerator achieves 28% less cost, 90% less responding time, an ASSR accuracy of 90%. Comparison exhibits that performance of the proposed system is greater than the conventional works, thereby demonstrating the friendly and affordable factor of the proposed HMI.

A New Binary-Halved Clustering Method and ERT Processor for ASSR System

This paper presents an automatic speech-speaker recognition (ASSR) system implemented in a chip which includes a built-in extraction, recognition, and training (ERT) core. For VLSI design (here, ASSR system), the hardware cost and time complexity are always the important issues which are improved in this proposed design in two levels: (1) algorithmic and (2) architecture. At the algorithm level, a newly binary-halved clustering (BHC) is proposed to achieve low time complexity and low memory requirement. In addition, at the architecture level, a new ERT core is proposed and implemented based on data dependence and reuse mechanism to reduce the time and hardware cost as well. Finally, the chip implementation is synthesized, placed, and routed using TSMC 90-nm technology library. To verify the performance of the proposed BHC method, a case study is performed based on nine speakers. Moreover, the validation of the ASSR system is examined in two parts: (1) speech recognition and (2) speaker recognition. The results show that the proposed system can achieve 93.38% and 87.56% of recognition rates during speech and speaker recognition, respectively. Furthermore, the proposed ASSR chip includes 396k gate counts, and consumes power in 8.74 mW. Such results demonstrate that the performance of the proposed ASSR system is superior to the conventional systems.

A Statistical Out-of-Speaker Detection Approach for Smart Home Voice-Control Scenario of Protective Warming Care on FPGA

In this paper, an Out-Of-Speaker (OOS) detection algorithm based on the statistical approach is newly proposed and embedded in the previous automatic speaker-speech recognition (ASSR) work on a FPGA platform. The proposed work is to build the unenrolled speaker recognition task which is not addressed in the previous ASSR system, and the experiment shows that the accuracy and the EER rate can reach to 86.7% and 19.8%, respectively, particularly in the cases of a few data for training and a short utterance (2s) for testing. For hardware realization, considered the limited resource FPGA platform, the proposed architecture only utilizes 29% of memory space, and the highly recursive computation of the proposed algorithm can be realized through the reuse design methodology to benefit the small-area design. The experimental results is shown that the unenrolled speaker rate is able to reach 88.3% accuracy, and the total number of utilized logical elements is only 13355 with memory usage is only 40.41K bytes, under a 50MHz working frequency of ALTERA DE2-70 FPGA.

A novel feature generation method based on nonlinear signal decomposition for automatic heart sound monitoring

This work presents a novel feature generation method for automatic heart sound monitoring system based on the nonlinear signal decomposition and the instantaneous characteristics of the decomposed components. In this work, first, the heart sounds (normal and abnormal) are decomposed by complementary ensemble empirical mode decomposition (CEEMD). Next, first five subcomponents are chosen empirically for further process. The instantaneous characteristics including instantaneous energy (IE) and frequency (IF) are estimated using Teager energy operator (TEO). After that, disregarding the energy and frequency information, total five IE versus IF maps are constructed. Then, the five IE-IF values transferred into a single feature space and using K-means algorithm, five mean values are selected. Further, a code book is constructed by vector quantization (VQ) method for the learning and future reference purpose. The experiment is performed on total 23 different classes of heart sounds including the normal and abnormal cases, collected from the Michigan Heart Sound and Murmur Database. The results indicate that the proposed method can achieve a recognition rate of 98%. Furthermore, a comparison with previous methods reveals that the proposed approach is superior. In contrast, the method is totally independent of any prior assumptions.

A high-accuracy ASR technique based on correlational weight analysis for elderly users

This paper proposes a robust template based on the previously proposed ECWRT (enhanced cross word reference template) for template-based ASR, by using correlational weight adjusting method to improve robustness against elderly speech variation named CWCWRT. This work addresses two vital issues: such as outlier rejection in training set and elimination of unwanted utterances which usually happen by the elderly people. Consequently, two main steps are investigated in this paper, firstly, correlational analyzing, and secondly, weight adjusting. For experiments, the corpus is built by 30 commands in Mandarin and English collected from three elderly (age 62±3 years) and three adults (age 22±2 years) having total 30 utterances for each of them. Two types of platforms including PC and GPCE063A embedded platform are conducted, both inside test and outside test are also applied. The results show that the average recognition rate for inside testis 97% in PC simulation and 90% in the embedded platform. The outside test results are 93% and 87% in two platforms respectively. The related and previous works including cross word reference template (CWRT) and ECWRT are also compared the comparison exhibit that the proposed CWCWRT gives higher robustness and accuracy than two baselines.

Fixed-Point Acceleration of Square Root and Logarithm Using Quadratic Regression for HTK Kernel Modules

This paper proposes a low-computation algorithm for logarithm and square-root in fixed-point domain. The algorithm only needs 3 ~ 6 coefficients to do inner-product of vectors which have three elements. Each computation only needs three fixed-point multiplications and two fixed-point additions to accomplish logarithm and square-root operations. According to the experimental results, the relative error is less than 0.075% and 0.6% for square-root and logarithm operation, respectively. Comparing with the CORDIC algorithm[1] [2] [3] [4], the proposed algorithm can provide the same precision and save 4 ~ 7 times additions, 33 ~ 40% lookup table operations, and 33% ~ 40% memory requirements, that indicates that the proposed algorithm is more efficient and appropriate for IC design.