Chih-Yuan Lu

Overlay target design and evaluation for SADP process

Overlay performance has been a critical factor for advanced semiconductor manufacturing for years. Over time these requirements become more stringent as design rules shrink. Overlay mark design and selection are the first two steps of overlay control, and it is known that different overlay mark designs will have different responses to process conditions. An overlay mark optimized for traditional process might not be suitable for SADP (self-aligned double patterning) technology due to changes in lithography and etching process conditions. For instance, the traditional BIB (box-in-box) target defined by the core mask becomes a template structure in SADP flow, the pitch and cycle of the overlay mark is further changed after spacer formation and core film removal hence the mark recognition and robustness have been challenging for the subsequent process layers. The comprehensive study on the methodology of overlay mark design and selection is still not available for SADP process. In this paper, various types of overlay marks were designed to comply with the SADP process to get rid of the weaknesses of traditional targets. TMU (total measurement uncertainty) performance was adopted to determine the optimal overlay marks for meeting production overlay control requirements in SADP process flow. The results have suggested the segmented marks outperform to non-segmented marks on image contrast as well as TMU.

Novel ATHENA mark design to enhance alignment quality in double patterning with spacer process

DPS (Double Patterning with Spacer) has been one of the most promising solutions in flash memory device manufacturing. Apart from the process complexity inherent with the DPS process, the DPS process also requires more engineering efforts on alignment technique compared to the single patterning. Since the traditional alignment marks defined by the core mask has been altered hence the alignment mark recognition could be challenging for the subsequent process layers. This study characterizes the process influence on the traditional ASML VSPM (Versatile Scribelane Primary Marks) alignment mark, and various types of sub-segmentations within VSPM marks were carried out to enable the alignment and find out the best performing alignment marks. The design of the transverse and vertical sub-segmentations within the VSPM marks is aimed to enhance the alignment signal strength and mark detectability. Alignment indicators of WQ (Wafer Quality), MCC (Multiple Correlation Coefficient) and ROPI (Residual Overlay Performance Indicator) were used to judge the alignment performance and stability. A good correlation was established between sub-segmentations and wafer alignment signal strength.

Process solutions for reducing PR residue over non-planar wafer

SAS (Self-Aligned Source) process has been widely adopted on manufacturing NOR Flash devices. To form the SAS structure, the compromise between small space patterning and sufficiently removing photo resist residue in topographical substrate has been a critical challenge as the device scaling down. In this study, photo simulation, layout optimization, resist processing and tri-layer materials were evaluated to form defect-free and highly extendible SAS structure for NOR Flash devices. Photo simulation suggested more coherent light source allowed the incident light to reach the trench bottom that facilitates the removal of photo resist. Mask bias also benefited the process latitude extension for residue-free SAS printing. In the photo resist processing, both lowering the SB (Soft Bake) and raising PEB (Post-Exposure Bake) temperature of photo resist were helpful to broaden the process window but the final pattern profile was not good enough. Thermal flow for pos-exposure pattern shrinkage achieved small CD (Critical Dimension) patterning with residue-free, however the materials loading effect is another issue to be addressed at memory array boundary. Tri-layer scheme demonstrated good results in terms of free from residue, better substrate reflectivity control, enabling smaller space printing to loosen overlay specification and minimizing the poly gate clipping defect. It was finally proposed to combine with etch effort to from the SAS structure. Besides it is also promising to extend to even smaller technology nodes.

Image-assistant OPC model calibration on 65nm node contact layer

This work compared the CD-based and image-assistant approaches for calibrating the OPC models. OPC models were first developed for 65nm-node memory contact layer and calibrated by contact test patterns with various ellipticities. The image-assistant model is a hybrid one calibrated by SEM contours and 1D measurement results, while the CD-based model calibration uses 1D measurement results as the sole data source. The fitting errors, model prediction ability and OPCed results were compared between these two models. Besides, the challenges on calibrating the edge-detection algorithm of the CD SEM images to the extracted contours of OPC tool were also discussed. Finally, the layouts corrected by CD-based and image-assistant models were written on a test mask for wafer-level comparison. The results displayed that the CD-based model showed smaller error on fitting and interpolation, but image-assistant model got improvement on extrapolation prediction of array-edge contact, unknown contact pattern and long contacts. The wafer-level comparison also revealed the image-assistant model outperformed to the CD-based model by smaller correction error on unexpected patterns.

Contact formation with extremely low proximity effect by double patterning technology

Contact hole within a NOR FLASH memory array is one of the most challenging features to print in the semiconductor manufacturing. It has been the key limiter of NOR FLASH memory scaling due to the difficulties involved in patterning the one-dimensional contact arrays and extremely stringent contact to gate overlay constraints. In this study, DPT (Double Patterning Technology) by ArF dry process was introduced for patterning NOR FLASH memory contact arrays. This approach has demonstrated a contact patterning with extremely low optical proximity effect for 50nm half-pitch with satisfied lithography process latitude and especially the circular contact shape can be maintained without compromise of NOR FLASH cell area. The novel hard mask scheme was the key enabler for this contact double patterning and this approach can be easily extended to ArF immersion lithography as a promising option for contact formation in leading-edge memory products.

Analysis of pattern density on process proximity compensation

The challenges of ever-smaller CD (Critical Dimension) budget for advanced memory product requires tight ACLV (Across-Chip Line-width Variation) control. In addition to the lithographic MOPC (Model-based Optical Proximity Correction) for DCD (photo CD) control, the process correction for etch proximity effect can no longer be ignored. To meet on our requirement on final CD accuracy for critical layer, a set of test pattern, that represents memory array in one of our critical layers, has been generated for both photo and etch process characterizations. Through the combination of different pattern-coverage areas in the test mask and wafer map design, various local (chip-level) pattern densities of 40%~70% and global (wafer-level) pattern densities of 35%~65% were achieved for optical and etch proximity study. The key contributors to the process proximity effect were identified and voluminous data has been extracted from the memory block like patterns for statistical analysis. The photo and etch proximity effects were hence modeled as function of memory block separation, local pattern density as well as global pattern density. Finally, the respective photo and etch proximity effects through model-based proximity correction and rule-based proximity correction were applied in a multi-step flow to products.

Wafer-edge defect reduction for tri-layer materials in BEOL applications

As the semiconductor feature size continues to shrink, the thickness of photo resist needs to be thinner and thinner to prevent resist features from collapse. Coupling with the need of high NA lithography for small feature patterning, both the reflectance control and the etch budget on resist thickness are becoming major challenges for lithographers. One way to simultaneously satisfy the needs of superior low reflectance, sufficient etch resistance and minimizing the resist feature collapse is adopting tri-layer lithography scheme. The tri-layer scheme has been successfully implemented in our manufacturing flow for FEOL (Front-End-of-Line) application. This work investigated the application of tri-layer scheme to BEOL (Back-End-of-Line) AlCu patterning. One critical problem met in this application is the defect that majorly originates from wafer edge after AlCu patterning. The defects were finally ascribed to the hump formation of Si-rich hard-mask by EBR (Edge Bead Removal) process. The hump of Si-rich hard-mask yields etch masking behavior during AlCu etch accordingly leads to pattern bridging or peeling of inorganic hard-mask after AlCu patterning. To reduce the defect, several evaluations were made to suppress the hump formation, including the EBR optimization, bake condition of Si-rich hard-mask, film stacking architecture of tri-layer by EBR rinse and surfactant additive added Si-rich hard-mask. A synergy effect among process factors has been proposed to effectively fix the defect problem around wafer edge.

A novel decomposition of source kernel for OPC modeling

The accuracy and efficiency of OPC (Optical Proximity Correction) modeling have become paramount important at the low k1 lithography. However the accuracy of OPC model has to compromise with the efficiency of model calibration and pattern correction, since the model accuracy is usually improved by using more kernels to represent the model but the runtime of model setup and pattern correction also increase as kernel count increasing. A novel decomposition of source kernel for OPC model calibration was presented in this study to maintain the model accuracy and preserve the OPC runtime at acceptable level. Firstly, the source kernel was decomposed into multiple subsource kernels and then the magnitude of electric field for each decomposed sub-source was modulated in frequency domain. Finally, the resultant source can be the combination of many different sub-sources to represent the tool-specific characteristics. The model accuracy, model stability and modeling runtime were compared among decomposed source, ideal source and measured source models. The results showed modeling residual RMS error, predictive capability of decomposed source can be reduced to be comparable to measured source and superior to the ideal source. As for the modeling efficiency, the decomposed source is up to 5 times faster than the measured source but just few percentages slower than the ideal source approach.

Intensity weighed focus drilling exposure for maximizing process window of sub-100-nm contact by simulation

In our previous study, we introduced the method of intensity weighting over various image planes for FLEX (Focus Latitude Enhancement eXposure) process. By higher energy weighting on the best focus image for the approach of triple focal plane exposure, it demonstrated higher contrast over wide focus range than conventional FLEX, accordingly achieved the better performance on DoF (Depth of Focus), EL (Energy Latitude), proximity and CD uniformity. However, this technique limits the production capability by the increased number of images. Thanks for all the technology developments on RET (Resolution Enhancement Technology) with tool functionality, which is related to focus drilling method in scanner system. Hence there have been several papers addressed the focus drilling technique with high frequency illumination source recently, the focus drilling technique enables more continual image planes over focus range on advanced step and scan system while scanning the image with single uniformity energy level over various focus ranges [2-3]. In this paper, the approach combining focus drilling with intensity weighting was introduced to strengthen the potential of process in step and scan system. Since the hardware for focus drilling and intensity weighting is not available in our study, weve only demonstrated the technical concepts through simulation by Prolith Ver. 9.31. To achieve the effect of intensity weighting on the focus range, weve been suggested new idea of application and applied some treatment on data from simulation tool. Simulation result on intensity weighted focus drilling achieved higher EL and DoF than the conventional focus drilling at the same focus range.

Multiple focal plane exposure in 248nm lithography to improve the process latitude of 110nm contact

Nowadays, RET (Resolution Enhancement Technology) is applied into lots of processes with special attention on the stage of development and manufacturing. Of the RET applications, FLEX (Focus Latitude Enhancement eXposure) [1- 2] is well known for 20 years and had shown that this method can enlarge the focus latitude on total window of DoF-EL (Depth of Focus and Exposure Latitude) through the benefit of gathering two or more exposure images with different focus planes. In double focal exposure, only focus level with even energy separation was considered in this study, and the image contrast flattening over wide focus range and contrast value lowering were demonstrated in this study by simulation. The lowering contrast level directly affects on physical resolution capability and proximity. But the area that is used to be a low contrast in single exposure has gained benefit from the image super-position, hence the variation of contrast over focus is much smaller by double focal exposure and wider DoF is achieved. As for triple image plane process, the process selections are more versatile than single and double exposure; for example, we can even superpose the images with different energy distributions. In this paper, several image plane combinations were first reviewed by contrast level and contrast variation through normalized focus by simulation for optimizing the process condition, and then experimental verifications were also carried out to compare the lithographic parameters, such as, depth of focus, exposure latitude, CD controllability and mask error enhancement factor, for our interesting 1-D contact.