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Thin Solid Films | 1996

Difference of Si nodules precipitating from Al-X wt.% Si (X=0.5 ∼ 3.3)

Chikage Noritake; Ichiharu Kondo; K. Kondo; Osamu Takenaka; Akira Kinbara

Abstract Si nodules that appear in the. Al-Si electrode of integrated circuits often reduce their reliability. We have been studying methods for reducing the Si nodules precipitated on an insulated film such as a BPSG film. In our previous study, we proposed a growth mechanism for Si nodules on the insulated film, based on the detailed analysis of the interface between the Si nodule and the insulated film [6]. In this paper, the relationship between the Si contents (X) of Al-X wt.% Si film and the generation of the Si nodules is discussed in relation to the developed growth mechanism of Si nodules on the insulated film. Al-X wt.% Si films (X=0.5,0.7,1.0,3.3 ) deposited on the insulated film by sputtering method are annealed at 723 K for 30 min according to the usual IC procedure. The Si nodules are observed by TEM, SEI (scanning electron image) and SEM. In the case of X=0.7 or more, Si nodules are precipitated on the insulated film, while in the case of X=0.5, no Si nodule is precipitated. According to the EDX analysis of the Si nodule/BPSG interface, it is observed that at the central part of the interface, an Si-0 layer is formed, and at the periphery, an Al-Si-P-0 layer is formed. It is thought that in the case of X=0.5, all of the Si nodules are dissolved in the AI film during annealing because the Si solubility in Al is 0.5 wt.% at 723 K according to the Al-Si phase diagram. While in the case of X>0.5 wt.%, Si nodules exist during annealing, Si nodules are precipitated on the BPSG film after annealing. In the case of X=0.7, Si nodules are grown on the BPSG film, while in the case of X-3.3, the Si nodules are grown both on the BPSG film and within the Al film. The difference is thought to come from the Si contents.


Archive | 1995

Semiconductor device with bump structure

Ichiharu Kondo; Chikage Noritake; Yusuke Watanabe


Archive | 2002

Method for manufacturing semiconductor power device

Mikimasa Suzuki; Chikage Noritake


Archive | 2011

SEMICONDUCTOR MODULE WITH COOLING MECHANISM AND PRODUCTION METHOD THEREOF

Chikage Noritake; Hiroaki Arai; Yoshiyuki Yamauchi; Yasuou Yamazaki; Naoki Sugimoto; Yasuyuki Sakai


Archive | 2007

Semiconductor device having tin-based solder layer and method for manufacturing the same

Kimiharu Kayukawa; Akira Tanahashi; Chikage Noritake; Shoji Miura


Archive | 2003

Method for manufacturing semiconductor device having controlled surface roughness

Yutaka Fukuda; Naohiko Hirano; Chikage Noritake; Shoji Miura


Archive | 2005

Method for manufacturing semiconductor device having solder layer

Chikage Noritake; Yoshitsugu Sakamoto; Akira Tanahashi; Hideki Toyota Okada; Tomomasa Yoshida


Archive | 2011

PRODUCTION METHOD OF SEMICONDUCTOR MODULE WITH RESIN-MOLDED ASSEMBLY OF HEAT SPREADER AND SEMICONDUCTOR CHIP

Chikage Noritake; Tsuyoshi Arai; Naoki Hiraiwa


Archive | 2009

Semiconductor module molded by resin with heat radiation plate opened outside from mold

Chikage Noritake; Takanori Teshima; Kuniaki Mamitsu


Archive | 2011

SEMICONDUCTOR MODULE WITH RESIN-MOLDED PACKAGE OF HEAT SPREADER AND POWER SEMICONDUCTOR CHIP

Chikage Noritake; Naoki Hiraiwa; Tsuyoshi Arai

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