Chiming Lai

Fabrication of Micro-Polymer Lenses With Spacers Using Low-Cost Wafer-Level Glass-Silicon Molds

A novel low-cost molding process to prepare polymer-based micro-lens arrays with spacers for optical applications was investigated in this paper. The process consists of the following steps: 1) hemispherical glass bubble arrays, used as the upper part of the molds, was prepared by combining a hot-forming process and a chemical-foaming process; 2) the silicon mold, used as the lower part of the molds, was fabricated by etching; 3) an anti-stick layer was coated on the concave surface of the glass mold; and 4) the lens material, UV-curable glue, was dispensed into the concave molds, followed by curing and de-molding. The optical properties of the lens were characterized by a profile meter and a beam analyzer. The results showed that the micro-polymer lens arrays with spacers were successfully prepared using the low-cost wafer-level glass-silicon mold. The results indicate that the micro-lenses have hemispherical structures and smooth surface.

Chip-on-board (COB) wafer level packaging of LEDs using silicon substrates and chemical foaming process(CFP)-made glass-bubble caps

In this paper, we investigate a novel Chip-On-Board (COB) process for wafer level LED packaging using micro glass-bubble caps and silicon substrates. The COB packaging process is firstly studied experimentally, which consists of the following steps. First, a silicon substrate with lead lines is prepared. Second, LEDs are mounted on the silicon substrate followed by wire-bonding. Third, phosphor is distributed uniformly onto the spherical inner wall surface of glass bubbles. Fourth, the spherical glass bubbles are filled with silica gel. Finally the LEDs on the silicon substrate are encapsulated by the spherical glass-bubble caps. The thermal performance of the LEDs using the COB technology is then simulated by ANSYS and tested. Results show that the COB process is demonstrated successfully and the packaged LED chip has a good thermal and optical performance. Results also indicate that the wafer level COB LED packaging technology using silicon substrates and CFP-made spherical glass-bubble caps would improve the reliability and optical performance of high power white light LEDs greatly.

Fabrication of low cost wafer-level micro-lens arrays with spacers using glass molds by combining a Chemical Foaming Process (CFP) and a Hot Forming Process (HFP)

This paper reports an innovative molding process for the fabrication of low cost wafer-level micro-lens array with spacers of optical applications. The concave mold for the micro-lens includes two parts: the upper glass mold and the under silicon mold. The upper glass mold was prepared by combining the Hot Forming Process (HFP) and the Chemical Foaming Process (CFP). The under silicon mold was prepared by etching. Specially designed concave structures were prepared on both parts. An anti-adhesion layer was formed on the surface of the concave mold. UV-light curable glue, the lens material, was injected into the concave mold and cured. Results show that wafer-level micro-lens arrays with spacers were successfully fabricated after de-molding the reusable mold. Samples of 6×6 micro-lens arrays with spacers, in diameter of 800μm and pitch of 2600μm, were prepared. Fabrication imperfection and design of micro-lens array was discussed.

A novel wafer level packaging for white light LED

After the first white light-emitting diodes (WLEDs) became commercially available, much attention has been paid to the development of WLEDs because of their extensive applications in solid lighting. Compared with traditional lighting, WLEDs have more advantages, such as high efficiency, long lifetime, fast response and environmental-friendliness [1-3]. It has been widely used in signals, displays and lighting. However, high price is still the main block for its wide application. As a new LED packaging solution, wafer level packaging(WLP) has attracted more and more interesting for whole semiconductor industry for predictable advantages over traditional packaging types, WLP is an as-know low cost packaging method, which has been demonstrated in IC (integrated circuit) industry already [4-5]. In this paper, a novel packaging for white LED, benefit from Si material and TSV array used in the wafer level LED package, the capability of thermal dissipation could be enhanced. Compared to the traditional LED, there are many advantages of this package, The advantages of this 3D integration package are:(1) good thermal diffusivity, (2) good light efficiency, (3) less footprint. The structure of the packaged LED was characterized, and light performance was tested according to standard LED testing method, and thermal resistance was simulated and tested, the result is close to Cree LED.

Study on volume production of uniform wafer-level micro glass cavities by a chemical foaming process (CFP)

In this paper, an improved chemical foaming process (CFP) for wafer-level glass cavities will be demonstrated for volume production in a clean room. First of all, suitable foaming agents transferring techniques are investigated to avoid powder pollution to the chips in a clean room. In addition, the precise controlling of the sizes of the glass cavities is studied theoretically and experimentally. The shapes, morphology and sizes of the glass cavities formed by the improved CFP are characterized by AFM and digital 3D microscopy. A theoretical model for precisely predicting the final shapes and sizes are established. Moreover, glass cavities with uniform structures and precisely controlled sizes at a 4-inch wafer are prepared successfully. The improved CFP will provide a novel volume-production technique for micro-machining of glass, which has many applications in MEMS and MOEMS.

Introducing FCA, a new alloy for Power Systems on a chip and Wafer Level Magnetic applications

On chip integrated inductors and transformers require novel and improved materials and CMOS-compatible Wafer Level Magnetics (WLM) deposition techniques. In this work we are presenting an Fe-Co based amorphous magnetic alloy, called FCA that was specifically designed and developed by Enpirion to be used for the first time in volume production for highly integrated and miniaturized power management electronics. The FCA properties that make it suitable for use in a real product are: stable permeability to frequencies higher than 20MHz, high electrical resistivity ρ>120 μΩ-cm, high magnetic saturation Bs>1.5T, and ultra-low coercivity Hc<;1. The fully CMOS-compatible FCA electro-deposition is carried out in JCAPs wafer production fab in China using customized electroplating equipment that was specifically developed for the FCA plating chemistry. A microinductor utilizing an FCA magnetic core is developed, characterized and integrated into a DC-DC converter. This work demonstrates a commercially viable and available to market 1Amp DC-DC switching converter operating at 18MHz with efficiency up to 90% that utilizes electroplated magnetic materials on wafer for the first time in the power management industry.

A study of novel wafer level LED package based on TSV technology

LED (light-emitting diode) has many advantages over traditional lighting source such as higher electrical efficiency, faster response, and free of hazardous, which has been attracting more and more interesting from all of world. LED technology has achieved remarkable progress during latest years already. However, high price is still the main block for its wide application. WLP (wafer level package) is an as-know low cost packaging method, which has been demonstrated in IC (integrated circuit) industry already. Wafer level package for LED is expected as a promising solution for reduction of total LED price. Aimed at low package cost, as well as good thermal and electrical performance, a novel wafer level LED package with TSV (through silicon via) interconnection and remote phosphor was studied. And structure of the packaged LED was characterized, and light performance was tested according to standard LED testing method.

Preparation of wafer-level LED packaging used uniform micro glass cavities by an improved Chemical Foaming Process (CFP)

Micro glass cavity has very important research values in many fields including Lighting Emitting Diode (LED) packaging, atomic devices, MEMS packaging and so on. In this study, an improved Chemical Foaming Process (CFP) have been investigated and uniform wafer-level micro glass cavities, which could be used in wafer-level LED packaging, have been prepared successfully by the proposed process. First of all, the fabrication process is introduced. Then the prepared uniform wafer-level semispherical glass cavity has been characterized by Atomic Force Microscopy (AFM) and mechanical shock test. And the result shows that the surface roughness of glass cavity is quite smooth which suits for optical applications as well as many other applications. At last, LED chip packaged with semispherical micro glass cavity on silicon substrate is presented.

Solution to leakage of polyimide-structural wafer level package

For handheld products, package size is required as small as possible, new packaging technology such as wafer level chip scale packaging (WLCSP), stacking die, 3D packaging is developed quickly. So far, wafer level packaging is realized in mass production and accepted by most of semiconductor enterprises. However, mechanical reliability is the great concern for WLCSP products usage. The primary driving force of the electrical failure is rapidly winding of circuit board due to high-accelerated strain. To improve the mechanical performance of the package, PI is introduced to buffer the stress, but PI also increases the risk of leakage aspect to electrical performance. In this paper, experiments were conducted to decrease the leakage by investigating several factors, including etching solution concentration, etching time, etching temperature and plasma. The result shows that wet etching process optimization only can decrease the leakage to 18nA, but using wet etching coupled plasma method, the leakage is dropped dramatically and as small as 0.0InA. A mode is proposed to explain the action mechanism of plasma on decreasing leakage.

Stress control of plasma enhanced chemical vapor deposited SiO 2 film in through silicon via process

Through silicon via is an essential element for three dimension integration. Excessive stress have potential effects on the reliability of the structure. One concern is the peeling problem of SiO2 layer. It was found that it is caused by the electroplated copper during later solder reflow process. We also found that it is possible to ameliorate the peeling problem by increasing the compressive stress in the SiO2. We found that the peeling problem is solved when SiO2 was deposited with higher compressive stress. Compared to 90% peeling off for compressive stress -20 MPa in the SiO2, Only 20% peeling off for compressive stress -40 MPa in the SiO2 and no peeling off for compressive stress -110 MPa and -150 MPa in the SiO2.