Chin-Fong Chiu

A new rail-to-rail comparator with adaptive power control for low power SAR ADCs in biomedical application

In this paper, a new IV rail-to-rail comparator is presented with low noise, high speed and low power consumption. We utilize current mirrors to overcome the kickback noise. A new adaptive power control (APC) technique is also proposed to minimize the power dissipation of the comparator. Moreover, it provides an optimized and stable power dissipation irrelative to process and bias variation. A prototype IV rail-to-rail SAR ADC for biomedical application has been implemented in 0.18μm TSMC CMOS technology. It consumes 2.86 μW at 250kS/s and the figure of merit is 85.7 fJ/conversion-step. It shows that this work efficiently reduces 52% to 80% power consumption of the dynamic comparator at 500kS/s to 125kS/s.

A Linear-Logarithmic CMOS Image Sensor With Pixel-FPN Reduction and Tunable Response Curve

This paper presents a high dynamic range (DR) linear-logarithmic (Lin-Log) CMOS image sensor (CIS) pixel with threshold voltage cancellation technique for pixel fixed pattern noise (PFPN) reduction. A tunable pixel response curve was applied for different environments. To avoid the gain loss of source follower in conventional APS structure, a column shared-amplifier with programmable gain was also applied. A prototype high DR Lin-Log CIS chip consisting of 100 × 100 5-T pixel array with n+/p-sub photodiode, a pixel area of 6 × 6 μm2, and 3.3 V operation was designed and fabricated in TSMC 0.18 μm CMOS 1P6M standard process. The measured results achieved a DR of 143 dB, a PFPN related to sensitivity in logarithmic response (rms/log-sensitivity) of 1.96%, and a PFPN related to full-swing in logarithmic response (rms/Vlog-swing) of 0.45%. Linear and logarithmic sensitivity were 651 mV/lux-s and 55 mV per decade of illumination, respectively, at 50 fps. The temporal noise and power consumption were 0.746 m Vrms and 1.88 mW, respectively.

Linear CMOS image sensor with time-delay integration and interlaced super-resolution pixel

This paper presents a high frame rate linear scan CMOS image sensor (CIS) with time-delay integration (TDI) technique and interlaced super-resolution (ISR) pixel to increase signal-to-noise ratio (SNR) and horizontal resolution. An adjacent pixel signal transfer (APST) methodology is adopted for efficient wire routing and reducing pixel complexity. 4T-APS is applied in pixel to achieve the snapshot function. A 128×8×2 interlaced super-resolution pixel array with a pitch of 6×6 um2, a fill factor of 26.99%, and 3.3V operation has been designed and fabricated in 0.18-um TSMC 1P6M CIS technology. Two 128×8 linear array are placed in an interlaced form with a half-pixel-pitch shift to achieve the super-resolution output. The measurement results of proposed linear scan sensor with 8 TDI stages and ISR technique demonstrate a SNR improvement of 10.3 dB, double horizontal resolution, and a power dissipation of 4.114uW per column at 1.6kfps.

Time-delay integration readout with adjacent pixel signal transfer for CMOS image sensor

This paper presents a time delay and integration (TDI) structure for CMOS image sensor (CIS) with adjacent pixel signal transfer (APST). The CCD-like TDI function is achieved in CIS by proposed APST without additional in-pixel device and minimum routing effort. The in-pixel integrated signal is transferred to adjacent pixel and summed up by an off-pixel column-shared unity-gain buffer. A 128×6 pixel array with 6×6μm2 pixel size has been designed and fabricated in TSMC0.18μm 1P6M CIS technology providing 6 TDI stages with fill factor of 23.1%. It achieves a signal to noise ratio (SNR) improvement of 13dB, a transfer efficiency of 99.6%, and a total power dissipation of 4.43 μW per column at 1.6K fps.

A 9.2b 47fJ/conversion-step asynchronous SAR ADC with input range prediction DAC switching

This paper presents a 10b 500KS/s asynchronous successive approximation register analog-to-digital converter (SAR ADC) with input range prediction DAC switching technique for low power applications. The proposed input range prediction DAC switching technique narrows down the traditional try-and-error range of the input signal to prevent unnecessary DAC switching, and the average switching energy is 90% more efficient than the conventional approach. A prototype is fabricated in 0.18um CMOS technology. With a single supply of 1V, it achieves an ENOB, SNDR and FoM of 9.24b, 57.3dB, and 47fJ/Conversion-step at 500KS/s sampling rate, respectively.

A 1.8V readout integrated circuit with adaptive transimpedance control amplifier for IR Focal Plane Arrays

A readout integrated circuit (ROIC) with adaptive transimpedance control (ATC) amplifier for Infrared Focal Plane Arrays (IR FPAs) is presented in this paper. The proposed ATC readout circuit is consisted of a front-end transimpedance amplifier (TIA) with an adaptive feedback capacitance. The output signal is fed to a comparator which determines a set of gain code (S0∼S1) to control the feedback capacitance selected from a capacitor array. A CMOS image sensor chip with 32×32 pixel array and 30×30µm2 pixel size has been designed and fabricated in 0.18µm CMOS technology. It achieves a 24dB improvement of dynamic range, a frame rate of 22 fps, a power-per-pixel of 5µW/pixel and the total power of 5.5mW, respectively. The proposed ATC amplifier provides an optimized solution for IR FPA with wide dynamic range (WDR) operated at 1.8V supply.

An information sensor with in-pixel-processing for geriatric nursing

A new concept of “information sensor” (IS) has been presented in this paper. IS is defined by integrating CMOS image sensor with in-pixel-processing capability of captured image. The output of IS is only the necessary information data for applications instead of image raw data. The purpose of IS is not only to provide a non-complex, low cost, less power consumption system for image information extraction, but also to reduce the risk of privacy releasing. The proposed sensor system has three operation modes as image-display, edge-detection and barycenter-locating. The image-display mode is the standard imager mode with raw data output. The other two modes are used to output the necessary information for locating the specified target (e.g. geriatric or aged individuals) for nursing. A 56×48 IS pixel array with pixel pitch as 25×25 um2 and 3.3V operation has been designed and implemented in 0.18-um TSMC CIS technology. The measured results of proposed IS chip demonstrate successful output with raw image, edge extraction and barycenter locating.

A 0.5 V, 14.28-kframes/s, 96.7-dB Smart Image Sensor With Array-Level Image Signal Processing for IoT Applications

This paper presents a smart image sensor with multiple operation modes, including edge extraction, multipoint tracking (MPT), and high-dynamic-range (HDR) imaging for wireless sensor nodes in Internet-of-Things applications. The pixel consists of a 0.5 V operated pulsewidth-modulation sensor for achieving HDR response and low fixed pattern noise. Array-level image signal processing is implemented using a local interpixel feedback network, in-pixel low power dynamic logics, and a corresponding peripheral with an event-driven hand-shaking readout. A prototype chip with a 64 × 64 CMOS image sensor (CIS) array is designed and fabricated in a TSMC 0.18-μm CIS technology. In the MPT mode, the measured tracking speed is 14.28 kframes/s with an error of 0.36 pixels and a tracking capability up to four points. In the HDR imaging mode, the achieved DR is 96.7 dB.

A column-parallel SA ADC with linearity calibration for CMOS imagers

This paper presents a 10-bit column-parallel successive approximation analog-to-digital converter (SA-ADC) with linearity calibration for CMOS imager. A multiple segmented charge redistribution capacitive digital-to-analog converter (MS-C-DAC) is utilized to reduce the DAC array size. A new linearity calibration method with adaptive reset configuration (ARC) of DAC is also proposed to solve the inherent mismatch issue of segmented DAC. The calibration technique ARC effectively eliminates three types of DAC error, i.e. (1) inaccurate serial capacitances, (2) parasitic capacitance on the charge conservation nodes, (3) mismatch of MSB capacitance. A prototype chip has been fabricated and verified in 0.18um CMOS technology. The new calibration method improves DNL from +5.62/-0.48 LSB to +0.33/-0.4 LSB, INL from +3.44/-4.93 LSB to +0.07/-1.81 LSB and SNDR from 46.63dB to 51.27dB at 240kS/s sampling rate. The whole chip consumes 35.46uW at a single 1.8V supply operation.

An image lag free CMOS image sensor with Constant-Residue Reset

A lag-free CMOS image sensor (CIS) with Constant-Residue Reset (CRR) operation is presented in this paper. It effectively eliminates image lag effect caused by the channel doping profile variation of transfer transistor and non-optimized pixel layout in the 4T-pixel. A prototype 160×120 CMOS imager has been designed and fabricated in 0.18um 1P4M CIS process. The experimental results demonstrated that the image lag effect is fully eliminated by CRR operation.