Chin-Hsing Kao

Performance improvement of SONOS memory by bandgap engineering of charge-trapping layer

A significant improvement in device performance and reliability characteristics of silicon-oxide-nitride-oxide-silicon (SONOS) Flash memory has been achieved. Superior endurance characteristic shows no sign of degradation even after 10/sup 6/ program/erase cycles and an extrapolated ten-year detection window of 1.4 V has been attained from retention measurement. The dramatic improvement results from a bandgap engineering of the SiN charge-trapping layer. With a gradual variation of the Si/N ratio from bottom to top of nitride film rather than uniform standard composition, a large number of highly accessible trapping levels are created in addition to the deepened barrier height between nitride and tunnel oxide that reduces back-tunneling probability. The proposed technique shall be valuable in pushing Flash memory technology into the next generation.

SONOS device with tapered bandgap nitride layer

A unique, band-engineered, configuration of the charge-trapping layer in silicon-oxide-nitride-oxide-silicon (SONOS) devices is proposed for high-density Flash memory applications. In this paper, a varying Si-N ratio in modified silicon nitride is obtained by controlling reaction gas flow-rate during deposition. This generates a graded composition profile from Si-rich at the bottom to N-rich at the top in a nitride film. The nonuniform composition profile of the silicon nitride layer corresponds to a tapered bandgap and results in significant improvement in device performance and reliability characteristics including operation window, cycling endurance and data retention. The dramatic improvement can be attributed to increased charge-trapping efficiency of the nitride layer since a significant number of highly accessible trapping levels are created in the tapered bandgap. In addition, the increased barrier height between the nitride and tunnel oxide layers also reduces back-tunneling probability and assists charge trapping. The SONOS device designed in this paper is suitable for next-generation Flash memory applications.

A simple systematic spiral inductor design with perfected Q improvement for CMOS RFIC application

In this paper, a systematic design procedure based on key factor analysis of the Q curve has been proposed. In addition to inductor design, we also present a technique that combines optimized shielding poly, and proton implantation treatment is utilized to improve the inductor Q value. The shielding effect of poly-silicon and the semi-insulating characteristics of proton-bombarded substrate have added a 37% and 54% increment to the Q value of the inductors, respectively. The combination of the two means has created a multiplication of their individual contribution rather than addition. The dramatic improvement of the Q value resulted from the doping level and film thickness optimization of a poly shield layer combined with a proton implantation treatment. A phenomenal Q-value increment as high as 122% of 4-nH spiral inductors can be realized. This technique shall become a critical measure to put inductors on a silicon substrate with satisfactory performance for Si-based RF integrated-circuit applications

An efficient noise isolation technique for SOC application

A highly efficient CMOS process technique of suppressing the transmission of high-frequency noise induced by spiral inductors, ultrafast-switching MOS gates, or supply ringing through silicon substrate has been attained. The isolated n/sup +/-pocket structure formed by a promising process technique designed in this work has proven to be most effective in guarding vulnerable devices from remnant high-frequency noise roaming in the substrate among the structures we have used in the experiment: p/sup +/ guard ring, proton implant, and pocket structures. Excellent noise suppression efficiency of -75 dB with source and sense separated by only 21 /spl mu/m at 1 GHz has been achieved for the test keys with n/sup +/-pocket structure in contrast to -38 dB at 1GHz of unprotected devices. The isolated n/sup +/-pocket structure has manifested itself to possess the potential of becoming a key technology for mixed-mode circuits in future success of Si-based wireless communication system-on-chip (SOC) applications.

Improved performance of Si-based spiral inductors

Conventional spiral inductors on silicon wafer have suffered low quality (Q) factor due to substrate loss. In this work, a technique that combines optimized shielding poly and proton implantation treatment is utilized to improve inductor Q-value. The optimized poly-silicon and proton-bombarded substrate have added 37% and 54% increment to the Q-value of inductors, respectively. If two techniques are combined, a phenomenal Q-value increment as high as 122% of 4-nH spiral inductors can be realized. The combination of the two means has created a multiplication of their individual contribution rather than addition. The technique used in this work shall become a critical measure to put inductors on silicon substrate with satisfactory performance for Si-based radio frequency integrated circuit applications.

Methods for noise isolation in RFCMOS ICs

Different process techniques of suppressing the transmission of high-frequency noise induced by fast-switching MOS gates through silicon (Si) substrate have been examined. The isolated n/sup +/-pocket structure formed by a new process technique designed in this work has proven to be most effective in guarding vulnerable devices from remnant high-frequency noise roaming in the substrate among the structures we have used in the experiment: p/sup +/ guard ring, proton implant, and pocket structures. The noise suppressing efficiency is -75 dB at 1 GHz of n/sup +/-pocket structure in contrast to -38 dB at 1 GHz of unprotected devices. The protecting structures should become a decisive measure for future success of Si-based radio frequency integrated circuit (RFIC) applications.

Deposition-Temperature Effect on Nitride Trapping Layer of Silicon–Oxide–Nitride–Oxide–Silicon Memory

A silicon nitride film is one of the most important factors for determining the trapping efficiency of nonvolatile silicon–oxide–nitride–oxide–silicon (SONOS) memory devices. In this work, we focus on the nitride-layer deposition at different temperatures by low-pressure chemical vapor deposition (LPCVD) and examine the trap levels through photoluminescence (PL) measurement. Moreover, using DC current–voltage (I–V) and capacitance–voltage (C–V) measurements, we investigate the electrical characteristics, breakdown characteristics, and the relationship between performance and trap-level depth. Our results show that the silicon nitride deposited by LPCVD at 830 °C has better performance and reliability. However, the charge-to-breakdown (QBD) quality of the nitride film deposited at 600 °C is better due to the suppression of the influence of the transition layer near the interface at the lower deposition temperature. In summary, this study can help researchers to understand the temperature effect on nitride-film deposition and the analysis of its electrical characteristics.

Comparison of electrical and reliability characteristics of different tunnel oxides in SONOS flash memory

The characteristics of polysilicon-oxide-nitride-oxide-silicon (SONOS) devices with different tunnel oxides are studied. The tunnel oxide fabricated by high-temperature oxide (HTO) with additional NO annealing treatment (HTO (NO*)) has better performance than that fabricated by HTO only and in-situ steam generated oxide (ISSG) including operation window, retention, and endurance. Besides, the properties of charge-to-breakdown are also observed. The study can provide a straightforward way of reliability for future flash memory application

Retention Reliability Improvement of SONOS Non-volatile Memory with N2O Oxidation Tunnel Oxide

The reliability characteristics of polysilicon-oxide-nitride-oxide -silicon (SONOS) devices with different thin tunnel oxides are studied. The tunnel oxynitride growth in a pure N2O ambient with high temperature has better performance than in a dry oxidation with N2 annealing treatment including leakage current, programming speed, read disturb and retention. Besides, the surface roughness and interface states between tunnel oxide and Si substrate are also observed by atomic force microscope (AFM) technique and charge-pumping method to evaluate interfacial nitrogen incorporation. The results show that the reliability of data retention obtained a significant improvement while maintaining good programming/erase performance and can provide a straightforward way of reliability improvement for future flash memory application

Endurance and Data Retention Improvement of Silicon–Oxide–Nitride–Oxide–Silicon Nonvolatile Semiconductor Memory Devices with Partially Bottom-Silicon-Rich Nitride Structure

A significant reliability improvement in silicon–oxide–nitride–oxide–silicon (SONOS) flash memory devices by band-gap engineering of the nitride layer has been attained. The gradually varied reaction gas flow rate during deposition has generated special nitride films with non uniform composition profiles and band gaps. As a result, SONOS devices with partially Si-rich nitride structures have exhibited superior cycling endurance, radiation hardness, and data retention compared with devices with a uniform standard nitride. The marked improvement can be attributed to the increased charge-trapping/detrapping efficiency of the nitride layer since a significant number of highly accessible trapping levels have been created in the nitride that has a graded band gap. In addition, the deepened barrier heights between the nitride and its surrounding oxides may also reduce undesirable charge-loss probability and assist in charge storage. Because the dimension of flash memory cells is continuously shrinking, the proposed technique will be valuable for mass storage applications.