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Dive into the research topics where Chin-Liang Wang is active.

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Featured researches published by Chin-Liang Wang.


IEEE Transactions on Signal Processing | 2005

Low-complexity selected mapping schemes for peak-to-average power ratio reduction in OFDM systems

Chin-Liang Wang; Yuan Ouyang

Orthogonal frequency-division multiplexing (OFDM) is an attractive transmission technique for high-bit-rate communication systems. One major drawback of OFDM is the high peak-to-average power ratio (PAPR) of the transmitters output signal. The selected mapping (SLM) approach provides good performance for PAPR reduction, but it requires a bank of inverse fast Fourier transforms (IFFTs) to generate a set of candidate transmission signals, and this requirement usually results in high computational complexity. In this paper, we propose a kind of low-complexity conversions to replace the IFFT blocks in the conventional SLM method. Based on the proposed conversions, we develop two novel SLM schemes with much lower complexity than the conventional one; the first method uses only one IFFT block to generate the set of candidate signals, while the second one uses two IFFT blocks. Computer simulation results show that, as compared to the conventional SLM scheme, the first proposed approach has slightly worse PAPR reduction performance and the second proposed one reaches almost the same PAPR reduction performance.


IEEE Transactions on Signal Processing | 2010

Novel Low-Complexity SLM Schemes for PAPR Reduction in OFDM Systems

Chih-Peng Li; Sen-Hung Wang; Chin-Liang Wang

The selected mapping (SLM) is a major scheme for peak-to-average power ratio (PAPR) reduction in orthogonal frequency division multiplexing (OFDM) systems. It has been shown that the complexity of the traditional SLM scheme can be substantially reduced by adopting the conversion vectors to replace the inverse fast Fourier transform (IFFT) operations. Each conversion vector is obtained by taking the IFFT of the phase rotation vector. Unfortunately, the corresponding phase rotation vectors of the conversion vectors in do not have equal magnitude, leading to significant degradation in bit error rate (BER) performance. This drawback can be remedied by adopting the perfect sequences as the conversion vectors. This paper presents two novel classes of perfect sequences, which are shown to be compositions of certain base vectors and their cyclic-shift versions. Then, two novel low-complexity SLM schemes are proposed by utilizing the special structures of the perfect sequences. The BER performances of both the proposed schemes are exactly the same as the traditional SLM scheme.


international symposium on circuits and systems | 1998

A parallel decoding scheme for turbo codes

Jah-Ming Hsu; Chin-Liang Wang

The recursive computations in the MAP-based decoding of turbo codes usually introduce a significant amount of decoding delay. In this paper, we present a method for reducing the decoding delay by means of segmenting a block into several sub-blocks, which are partially overlapped. The proposed sub-block segmentation scheme allows for the parallel decoding of each component code by using several sub-block decoders. The number of steps for the recursive computations in each sub-block decoder is reduced to O(N/W), where W is the number of segmented sub-blocks. The decoding delay is approximately one-Wth that of a conventional MAP-based turbo-coding system. The cost paid is a slight degradation in bit error rate performance and a reasonable increase in hardware complexity.


IEEE Transactions on Circuits and Systems for Video Technology | 1995

New systolic array implementation of the 2-D discrete cosine transform and its inverse

Yu-Tai Chang; Chin-Liang Wang

A new systolic array without matrix transposition hardware is proposed to compute the two-dimensional discrete cosine transform (2-D DCT) based on the row-column decomposition. This architecture uses N/sup 2/ multipliers to evaluate N/spl times/N-point DCTs at a rate of one complete transform per N clock cycles, where N is even. It possesses the features of regularity and modularity, and is thus well suited to VLSI implementation. As compared to existing pipelined regular architectures for the 2-D DCT, the proposed one has better throughput performance, smaller area-time complexity, and lower communication complexity. The new idea for the 2-D DCT is also extended to derive a similar systolic array for the 2-D inverse discrete cosine transform (IDCT). Simulation results demonstrate that the proposed 2-D DCT and IDCT architectures have good fixed-point error performance for both real image and random data. As a consequence, they are useful for applications where very high throughput rates are required. >


IEEE Transactions on Signal Processing | 2000

Efficient VLSI architectures for fast computation of the discrete Fourier transform and its inverse

Ching-Hsien Chang; Chin-Liang Wang; Yu-Tai Chang

In this paper, we propose two new VLSI architectures for computing the N-point discrete Fourier transform (DFT) and its inverse (IDFT) based on a radix-2 fast algorithm, where N is a power of two. The first part of this work presents a linear systolic array that requires log/sub 2/ N complex multipliers and is able to provide a throughput of one transform sample per clock cycle. Compared with other related systolic designs based on direct computation or a radix-2 fast algorithm, the proposed one has the same throughput performance but involves less hardware complexity. This design is suitable for high-speed real-time applications, but it would not be easily realized in a single chip when N gets large. To balance the chip area and the processing speed, we further present a new reduced-complexity design for the DFT/IDFT computation. The alternative design is a memory-based architecture that consists of one complex multiplier, two complex adders, and some special memory units. The new design has the capability of computing one transform sample every log/sub 2/ N+1 clock cycles on average. In comparison with the first design, the second design reaches a lower throughput with less hardware complexity. As N=512, the chip area required for the memory-based design is about 5742/spl times/5222 /spl mu/m/sup 2/, and the corresponding throughput can attain a rate as high as 4M transform samples per second under 0.6 /spl mu/m CMOS technology. Such area-time performance makes this design very competitive for use in long-length DFT applications, such as asymmetric digital subscriber lines (ADSL) and orthogonal frequency-division multiplexing (OFDM) systems.


IEEE Transactions on Communications | 2009

Novel conversion matrices for simplifying the IFFT computation of an SLM-based PAPR reduction scheme for OFDM systems

Chin-Liang Wang; Sheng-Ju Ku

There have been a set of conversion matrices proposed recently by Wang and Ouyang to simplify the inverse fast Fourier transform (IFFT) computation involved in the selected mapping (SLM) scheme for reduction of the peak-to-average power ratio (PAPR) in orthogonal frequency division multiplexing (OFDM) systems. As compared to the conventional SLM scheme, the modified approach achieves close PAPR reduction with much lower complexity but degraded bit error rate (BER) performance. In this paper, we propose a new set of conversion matrices for the SLM scheme such that the complexity can be reduced without sacrificing the BER performance. It is shown that the improved SLM method has better BER performance and lower complexity than the previous work by Wang and Ouyang, at the cost of a slight PAPR reduction loss.


IEEE Transactions on Wireless Communications | 2010

A Reduced-Complexity PTS-Based PAPR Reduction Scheme for OFDM Systems

Sheng-Ju Ku; Chin-Liang Wang; Chiuan-Hsu Chen

In this paper, a reduced-complexity partial transmit sequences (PTS) scheme is proposed to resolve the intrinsic high peak-to-average power ratio (PAPR) problem of orthogonal frequency division multiplexing (OFDM) systems. In the proposed PTS scheme, a cost function Qn is generated by summing the power of the time-domain samples at time n in each subblock. Only those samples with Qn greater than or equal to a preset threshold are used for peak power calculation during the process of selecting a candidate signal with the lowest PAPR for transmission. As compared to the conventional PTS scheme, the proposed one achieves almost the same PAPR reduction performance with much lower computational complexity.


global communications conference | 2003

A low-complexity peak-to-average power ratio reduction technique for OFDM systems

Chin-Liang Wang; Ming-Yen Hsu; Yuan Ouyang

One major drawback of orthogonal frequency division multiplexing is the high peak-to-average power ratio (PAPR). The selective mapping (SLM) approach provides good performance for PAPR reduction, but it may suffer from the high computational complexity of the bank of inverse fast Fourier transforms (IFFTs). We propose two low-complexity conversions to replace half of the IFFTs in the SLM method. Computer simulation results and complexity analyses show that, with the two proposed conversions, we can reduce about half of the computational complexity of the SLM approach and get better performance for PAPR reduction.


Computer Communications | 2009

Design of an adaptive positioning system based on WiFi radio signals

Yih-Shyh Chiou; Chin-Liang Wang; Sheng-Cheng Yeh; Ming-Yang Su

With the remarkable advances in wireless networking and pervasive computing, there have been an increasing need to figure it into LBS (location-based services) applications. This paper proposes an adaptive positioning system for the mobile terminal (MT) localization using the radio propagation modeling (RPM) and Kalman filtering (KF) according to the measurements of signal-to-noise ratio (SNR) information between indoor IEEE 802.11b (WiFi) APs and reference points (Tags). Comparing with the conventional empirical method (such as the fingerprinting method), the adaptive RPM algorithm can perform on-line calibration in real dynamic environments and reduce the number of training points. Additionally, the KF algorithm is used to track the location of MTs, where the observation information is extracted from the empirical and RPM positioning methods. The numerical simulations and experimental results show that not only the calibrating and positioning method of the RPM algorithm can improve the accuracy of an indoor WiFi locating system and alleviate the phenomenon of aliasing in the signal space, but also the estimating and tracking method of the KF algorithm can overcome the problem of the aliasing and reduce the positioning error with smaller sampling time.


IEEE Transactions on Image Processing | 1998

A new two-dimensional block adaptive FIR filtering algorithm and its application to image restoration

Terence Wang; Chin-Liang Wang

This paper presents a new two-dimensional (2-D) optimum block stochastic gradient (TDOBSG) algorithm for 2-D adaptive finite impulse response (FIR) filtering. The TDOBSG algorithm employs a space-varying convergence factor for all the filter coefficients, where the convergence factor at each block iteration is optimized in a least squares sense that the squared norm of the a posteriori estimation error vector is minimized. It has the same order of computational complexity as another 2-D optimum block adaptive (TDOBA) algorithm. Computer simulations for image restoration show that the TDOBSG algorithm outperforms the TDOBA algorithm and other related algorithms in terms of objective and/or subjective measures.

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Hung-Chin Wang

National Tsing Hua University

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Dong-Shing Wu

National Tsing Hua University

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Sheng-Ju Ku

National Tsing Hua University

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Ting-Nan Cho

National Tsing Hua University

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Yih-Shyh Chiou

National Tsing Hua University

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Yu-Tai Chang

National Tsing Hua University

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Yuan Ouyang

National Tsing Hua University

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Jah-Ming Hsu

National Tsing Hua University

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Terence Wang

National Tsing Hua University

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Chiuan-Hsu Chen

National Tsing Hua University

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