Ching-Yuan Wu

A simple interfacial-layer model for the nonideal I-V and C-V characteristics of the Schottky-Barrier diode

Abstract An interfacial-layer theory considering the nonequilibrium generation-recombination mechanism of the real interface states for Schottky-barrier diodes is presented. It is shown in the theory that the soft behavior of the reverse I - V characteristics associated with the observed nearly ideal C −2 - V characteristics can be modeled in terms of the interfacial-layer capacitance in a consistent manner, and that the nonideality of the forward I - V as well as C −2 - V characteristics should be attributed to the transition from the metal—controlled to semiconductor (majority carrier)—controlled occupancy of the interface states. The experimental verification for the theory is done by comparing the density distribution of the interface states in the semiconductor bandgap extracted from the nonideal forward I – V characteristics of the fabricated AlpSi and AlnSi Schottky barrier diodes with those directly measured by the multifrequency admittance methods. Excellent agreement from these comparisons strongly supports the physical validity of our theory.

A characterization model for ramp-voltage-stressed I-V characteristics of thin thermal oxides grown on silicon substrate

Abstract A theoretical model considering the effects of Fowler-Nordheim tunneling, image-force lowering, first-order trapping kinetics and impact ionization has been developed to characterize the ramp-voltage stressed current-voltage characteristics of thin oxides grown on silicon substrate. Based on the developed model, physical parameters of thin oxides such as effective total trapping density, trap capture cross section, recombination capture cross section and dielectric breakdown field can be extracted from the measurements. In general, the dielectric field strength of the oxide can be enhanced by increasing the amount of traps, which is especially important when the effective total trapping density is above 1013 cm−2. Besides, smaller leakage current across thin oxide can be obtained with larger effective total trapping density and trap capture cross section. The recombination capture cross section is found to be in the order of 10−15–10−14 cm2 for thin SiO2 ranging from 92 to 196 A. The dielectric field strength is enhanced and the leakage current is reduced as the trapped electron centroid shifts toward the cathode electrode, however, this is less prominent when the effective total trapping density is ⩽1012 cm−2.

THE OPEN-CIRCUIT VOLTAGE OF BACK-SURFACE-FIELD (BSF) P-N-JUNCTION SOLAR-CELLS IN CONCENTRATED SUNLIGHT

Abstract Simple analytical expressions for the open-circuit voltage of the n + − p − p + and p + − n − n + BSF solar cells, which are valid for both the low- and high-levels of optical illumination, are derived. Based on the principle of superposition the open-circuit voltage of both the n + − p − p + and p + − n − n + solar cells are expressed in terms of the short-circuit current and the known saturated dark current. Effects of the high-low junction doping, the energy-gap shrinkage, and the dimensions of the BSF solar cells on the open-circuit voltage are included. The numerical results of the derived expressions are found to be in good agreement with the exact numerical analysis of Fossum et al . The optimal design considerations based on the known characteristics of the open-circuit voltage are also discussed.

AN ANALYTIC AND ACCURATE MODEL FOR THE THRESHOLD VOLTAGE OF SHORT CHANNEL MOSFETS IN VLSI

Abstract Based on the two-dimensional Poisson equation, the surface potential distribution along the surface channel of a MOSFET has been analytically derived by assuming negligible source and drain junction depths and its minimum potential is then used to determine the threshold voltage. The existence of a minimum surface potential point along the channel of a MOSFET under an applied drain bias is consistent with the numerical results of the two-dimensional analysis. The effects of finite source and drain junction depths have been elegantly included by modifying the depletion capacitance under the gate and the resulted threshold voltage model has been compared to the results of the two-dimensional numerical analysis. It has been shown that excellent agreement between these results has been obtained for wide ranges of substrate doping, gate oxide thickness, channel length (

A new method for computer-aided optimization of solar cell structures

Abstract A new method for truly optimizing the design of intrinsic solar-cell structures has been established. To support the proposed method, a device modeling technique specialized for n+p solar cells with uniform doping has been developed, and the constrained optimization technique extended from Rosenbrocks algorithm has been implemented. All parameters to be optimized are simultaneously adjusted in a systematic manner, resulting in a truly optimum design. Several design examples for n+−p solar cells, such as maximizing cell efficiency and minimizing cell thickness while maintaining the acceptable characteristics, have been used to demonstrate the validity of the proposed method. Moreover, this method has also been successfully applied to the optimum design of other solar cell structures.

AN ACCURATE MOBILITY MODEL FOR THE I-V-CHARACTERISTICS OF N-CHANNEL ENHANCEMENT-MODE MOSFETS WITH SINGLE-CHANNEL BORON IMPLANTATION

Abstract In this paper we develop an analytical mobility model for the I–V characteristics of n-channel enhancement-mode MOSFETs, in which the effects of the two-dimensional electric fields in the surface inversion channel and the parasitic resistances due to contact and interconnection are included. Most importantly, the developed mobility model easily takes the device structure and process into consideration. In order to demonstrate the capabilities of the developed model, the structure- and process-oriented parameters in the present mobility model are calculated explicitly for an n-channel enhancement-mode MOSFET with single-channel boron implantation. Moreover, n-channel MOSFETs with different channel lengths fabricated in a production line by using a set of test keys have been characterized and the measured mobilities have been compared to the model. Excellent agreement has been obtained for all ranges of the fabricated channel lengths, which strongly support the accuracy of the model.

Barrier height enhancement of the Schottky barrier diode using a thin uniformly-doped surface layer

Abstract An analytic model for the barrier height enhancement of the Schottky barrier diode with the Mnp (or Mpn) structure, which considers the uniformly doped surface layer and the surface properties of the metal-semiconductor system, is presented. The maximum potential barrier and its precise location including the effect of the image-force potential have been calculated, which shows that the effective barrier height for the majority carriers without considering the image-force lowering will give erroneous predictions if the doped surface layer is very shallow or lightly doped. The built-in voltage of the Mnp structure based on the interfacial layer theory has also been calculated, which gives the exact dependence of the built-in voltage on the interface properties of the metal-semiconductor contact and the dose of the doped surface layer. Numerical results of the developed model have been computed and discussed, which may serve as the guide for the fabrication of the Schottky barrier (SB) and MIS solar cells with higher barrier height.

Physical model for characterizing and simulating a FLOTOX EEPROM device

Abstract A physical model has been developed to analyze the dynamic characteristics of a FLOTOX EEPROM device. The effects of the structural parameters such as the area and thickness of the tunneling-oxide and interpoly-oxide layers are characterized by a coupling ratio to describe the discrete programming or erasing operation. The physical parameters including the electron trapping and positive-charge generation effects are used to describe the endurance and retention operations of an EEPROM device. Computer simulations based on this model have been performed to analyze the operations of an EEPROM device, including the effects of three different programming/erasing input voltage waveforms (pulse, exponential rise and triangular). A method for protecting an EEPROM device from overshooting or undershooting during programming or erasing operation is proposed. Therefore, the proposed model can be used as a computer-aided-design (CAD) tool for device design and an efficient simulation tool for describing the dynamic operation and reliability of an EEPROM device.

A new computer-aided simulation model for polycrystalline silicon film resistors

Abstract A general transport theory for the I–V characteristics of a polycrystalline film resistor has been derived by including the effects of carrier degeneracy, majority-carrier thermionic-diffusion across the space charge regions produced by carrier trapping in the grain boundaries, and quantum mechanical tunneling through the grain boundaries. Based on the derived transport theory, a new conduction model for the electrical resistivity of polycrystalline film resitors has been developed by incorporating the effects of carrier trapping and dopant segregation in the grain boundaries. Moreover, an empirical formula for the coefficient of the dopant-segregation effects has been proposed, which enables us to predict the dependence of the electrical resistivity of phosphorus-and arsenic-doped polycrystalline silicon films on thermal annealing temperature. Phosphorus-doped polycrystalline silicon resistors have been fabricated by using ion-implantation with doses ranged from 1.6 × 1011 to 5 × 1015/cm2. The dependence of the electrical resistivity on doping concentration and temperature have been measured and shown to be in good agreement with the results of computer simulations. In addition, computer simulations for boron-and arsenic-doped polycrystalline silicon resistors have also been performed and shown to be consistent with the experimental results published by previous authors.

On the forward current-voltage characteristics of p+-n-n+ (n+-p-p+) epitaxial diodes

The forward-biased current-voltage characteristics of p+-n-n+ and n+-p-p+ epitaxial diodes are derived theoretically. Effects of the energy-gap shrinkage, the high-low junction built-in voltage, the high-level injection, and the minority-carrier life time on the forward-biased current-voltage characteristics are included. Good agreements between the theoretically derived results and the experimental data of Dutton et al. are obtained. The developed theory predicts that the leakage of the high-low junction is dominated by the recombination of minority carriers in the highly doped substrate, not by the recombination of minority carriers in the high-low space charge region, which is opposite to the previous prediction of Dutton et al.