Chongyong Yin

Reducing configuration contexts for coarse-grained reconfigurable architecture

In this paper, a configuration context reduction method for coarse-grained reconfigurable architecture (CGRA) is proposed. The proposed method exploits the structure correlation of computation tasks that are mapped onto CGRA and reduce the redundancies in configuration context. Experimental results show that the proposed method can averagely reduce the configuration context size up to 57% and speed up the execution up to 28.7%.

Compiler framework for reconfigurable computing system

A C compiler framework for reconfigurable computing system (RCS) is proposed to compile the applications written in high-level programming languages. The compiler extracts the data parallelism at instruction level in a given application, and produces the DFG generation, template automatically generating, template scheduling and mapping phase to generate configuration code for RCS. Experiment on a real multi-media application shows that, compared with NAPA C, SA-C, the proposed compiler can speedup the application by leveraging the RCA without the knowledge about physical level. Moreover, this compiler does not require the programmer to start with a specific parallel programming language, and possess more universal and flexible than Chimaera C compiler, and Garp C compiler.

Energy-aware task partitioning and scheduling algorithm for reconfigurable processor

Extending the battery runtime is very important for battery-powered reconfigurable processor, for it has the character of both high energy consumption and limited energy supply. In this paper, we try to find a method to extend the battery lifetime by partitioning and scheduling the task wisely. A good task partitioning scheme can optimize the energy consumption in hardware system, while a good sub-task scheduling scheme can minimize the energy dissipated in the nonlinear characters of the battery. By using the algorithm proposed in this paper, we can lower the energy consumed by hardware system and the nonlinear characters of the battery, thus we can obtain a longer battery lifetime. Experiments show that our algorithm has an average 20.38% better performance than LPA and an average 15.8% better performance than GPA in optimizing battery consumption.

Performance evaluation modeling for reconfigurable processor

Performance evaluation is very important for reconfigurable processor, for we can estimate the approximate performance before we actually run a program on the system hardware. In this paper, we try to find a new method to evaluate the system performance by simply analyzing the configuration contexts. With a C++ evaluation model constructed, we can extract the effective information from the configuration files and get the system performance rapidly, based on careful timing analysis. Experiments show that the evaluation models results and the simulation results match fairly well, and time cost will also be saved significantly, especially when the computing task grows more complex.

Template-based compilation for coarse-grained reconfigurable processor

The Compiler is very important to facilitate the use of reconfigurable processor. In this paper, a template-based compilation mechanism is proposed for coarse-grained reconfigurable processor. Based on template extraction and template matching, the proposed compilation mechanism can synthesize the executables for reconfigurable processor automatically. Experimental results show that the template-based compilation can significantly improve the execution performance and reduce the configuration-context size of the executables, compared with the operator-based compilation1.

A parallel implementation of MP3 decoding algorithm on Reconfigurable Computing systems

This paper describes a reconfigurable computing system, which consists of a general-purpose ARM processor and reconfigurable cells array (RCA). A novel mapping mechanism which makes data-parallelism instructions operate on RCA has been proposed to map and implement MP3 audio decoding algorithm containing intrinsic data-parallelism operations. The communication interface between ARM processor and RCA is implemented efficiently using the standard ARM assembly language. With the standard ARM C compiler, the hybrid decoding source files in which assembly language embedded are compiled to standard ARM machine instructions. The average decoding time of each frame is improved to 17.9 ms, and enhanced approximately 10% to which decoding time per frame is 20 ms, when the sampling frequency and bit-rate are 44.1 KHZ and 128 kbps, respectively.