Choon Heung Lee

A study on the rheological characterization and flow modeling of molded underfill (MUF) for optimized void elimination design

The molded underfill (MUF) process has a lot of advantages compared with capillary underfill process in view of reduction of process, cycle time of process, material and equipment cost since this application utilizes the conventional mold materials and equipment systems. But the extremely narrow gap at the underfill area for flip-chip bonding make it difficult to get stable MUF material set and appropriate processing conditions because of the severe void trapping problem. In this paper, the MUF process of flip-chip package on package (POP) is investigated. The rheological and cure- kinetic parameters of commercial MUF compound are acquired using parallel plate rheometer and dynamic DSC (differential scanning calorimeter) analysis. The experimental results showed severe void at the underfill area for both top- left and bottom-right pin type gate locations. The modeling results by full 3D mold filling simulation show good agreement with the actual void occurring area investigated by the SAT pictures. Applying the benchmarked constitutive relations and finite elements model, seven kinds of different gate types and locations are tried, but the void trapping is not completely removed. To resolve void trapping phenomena of current flip-chip structure, we devised a proprietary mold design. From the modeling results, the void trapping zone under the large die are effectively removed through the optimized design. From this study, we can conclude that the optimized mold design will be very effective on the elimination of void in the underfill area for flip-chip MUF processing.

Below 45nm low-k layer stress minimization guide for high-performance flip-chip packages with copper pillar bumping

In this paper, the FEM based various parametric studies such as packaging material and structural effects, under bump metallization and passivation structures and material property effects on the low k layer are investigated for the flip-chip packaging with Cu pillar interconnection. The results showed that the stress of the low k layer is directly concerned wirh the CTE mismatch between low k die and substrate constrained by Cu pillar and maximized at the bump near the die corner after flip chip attach process before underfill. The stress contour shows that the low k area is affected by both tensile stress and compressive stress. The experimentally inspected low k damaged area showed half moon shape which reveals the failure mode is closely related with the tensile stress near the Al to Cu pillar interface. The comparison results show that the Cu pillar has 20% higher stress than lead free solder and 40% than eutectic solder case. The structural DOE shows that the reducing flip-chip die and substrate thickness and also reducing passivation opening cases showed effective for reducing low k stress after flip chip attach. After underfill and mold or MUF only process, stress change of low k layer showed good agreement to the CTE variation of underfill or MUF which means thermal expansion of underfill / MUF is governing factor for low k stress for the after assembly. Compared with CUF, MUF which has lower CTE than CUF showed relatively lower stress on the low k layer. By applying optimized structure and material properties of package, UBM and passivation layers, the stress of the low k layer can be reduced to the relatively safe level where the stress is lower than the eutectic solder applied case of the reference structure.

Study of FC M BGA with low CTE core substrate

Amkors FCMBGA, flip chip package based on transfer molding for high performance device was developed and introduced to industry in 2008[1,2]. During the molding process, bump deformation was not significant, and voids were not observed under flip chip die. Coplanarity with a low Coefficient of Thermal Expansion, CTE, substrate construction was similar to a single piece lidded package construction. Coplanarity at high temperature did not change significantly with low CTE substrate compared to standard substrates. The flip chip package with molding passed reliability test such as Moisture Resistance Testing, MRT, and Thermal Cycling, TC 1500 cycles. No delamination or cracks were observed.

A Cost-Effective MEMS Cavity Packaging Technology for Mass Production

Cost effective microelectromechanical system (MEMS) packaging methods have been required, because the cost portion of the MEMS package is more than 80% of the manufacturing cost of a MEMS device. For this reason, cost-effective MEMS packaging is proposed in this paper for mass production using copper (Cu) lead frames (L/F) as a preplated frame (PPF). Package types include an epoxy molding compound (EMC) cavity wall and an on-frame type. The EMC-cavity package consists of a substrate, a cavity wall and a flat lid on top of the cavity. The on-frame package has a folded lid without a cavity wall. Finite element method (FEM) numerical modeling is performed to anticipate the mechanical warpage and stress of the packages. Assembled MEMS cavity packages were tested for wire pulling, lid pulling, hermetic test, and reliability tests in order to prove the feasibility of this packaging. The wire bonding strength was improved by 40% using plasma cleaning before wire bonding. Through a lid pulling test, a lid bonding strength of 2.40 kgf on average was obtained using an epoxy adhesive. Finally, all samples of the packages passed the reliability tests of the TC, HAST, and HTST, standardized by Joint Electron Device Engineering Council (JEDEC). Also, this cavity package showed excellent hermeticity through leak tests.

Rheological characterization and full 3D mold flow simulation in multi-die stack CSP of chip array packaging

According as high density packaging options such as 2 or more die stacking or package stacking technologies are developed, the major mold process related quality concerns such as incomplete mold, exposed wires and wire sweeping are increased because of their narrow spaces between die top and mold surface and increased wiring density. So, to verify those concerns, full 3D rheokinetic simulation of mold flow has been investigated for 3 die stacking structure of 4 times 4 mold array, 294LD case. The rheological parameters of commercial epoxy molding compound (EMC) were acquired through the slit-die rheometer and DSC (differential scanning calorie-meter) analysis. It is found that the severe void problem is one of the challenging factors in the thin and multi-die stack packaging to determine its manufacturability. To investigate the effect of different gate types, the molding options with four different gates were evaluated. The center gate showed most severe voids but corner gate showed relatively better void performance. But in case of the wire sweeping experiment and prediction results, the center gate type had less wire sweeping than the corner gate type. In the rheological simulation results, the corner gate case indicated increased velocity, shear stress and mold pressure near to the gate inlet and final filling zone. The experimental case study and the mold filling simulation showed good match on the mold external void and wire sweeping related prediction

MEMS packaging technology using a cavity structure for mass production

Lower cost package for microelectromechanical systems (MEMS) have been required, because the cost portion of the MEMS package is more than 30% of the cost of a MEMS product. For the reason, cost effective MEMS packaging platforms are proposed in this paper for high volume production. Two package platforms are developed using an epoxy molding compound (EMC) onto copper (Cu) pre-plated lead frames (L/F). One is a cavity wall type with attaching a flat lid. The other is an in-frame type with attaching a folded cap lid. Finite element method (FEM) numerical modeling is performed to anticipate the mechanical warpage and stress of the packages. The finally assembled packages are tested for wire pulling, lid pulling, hermetic test, and reliability tests. The wire bonding strength was improved in about 40% using plasma cleaning before wire bonding. Through a lid pulling test, the lid bonding strength of 2.40 kgf in average was obtained using an epoxy adhesive. Finally, all samples of the packages passed the reliability tests of the TC, HAST and HST, standardized by JEDEC (joint electron device engineering council). Also, this cavity package showed excellent hermeticity through leak test.

Board level reliability assessments of package on package

In spite of a great success of stacked package (PoP) in the market, some reliability issues about package on package (PoP) have been raised by several customers. To guarantee a high reliability in board level performances, many process and material developments are attempted. In the material developments, low silver contented solder alloys are adopted for higher board level drop performances. In OSP substrate pad finish, Sn/1.2Ag/0.5Cu/0.05Ni solder is applied and in Ni/Au substrate pad finish, Sn/1.0Ag/0.5Cu solder is adopted for higher reliabilities. 2nd level underfill is also adopted for higher drop performances but in this case, board level temperature cycle performance is deteriorated. To accomplish of higher board level performances both in temperature cycle and drop test, higher Tg & low CTE underfill materials are developed In the process developments, stacking materials and processes are developed. Board level reliabilities of pre- stacking & SMT stacking process is evaluated and paste and flux materials for top package stacking process are also evaluated. This paper discusses about board level reliabilities in temperature cycle and drop tests with various material and process combinations - especially, solder alloys, substrate pad finish, 2nd level underfill, stacking method and stacking materials.