Chris Chan

Getting More From the Semiconductor Test: Data Mining With Defect-Cluster Extraction

High-volume production data shows that dies, which failed probe test on a semiconductor wafer, have a tendency to form certain unique patterns, i.e., defect clusters. Identifying such clusters is one of the crucial steps toward improvement of the fabrication process and design for manufacturing. This paper proposes a new technique for defect-cluster identification that combines data mining with a defect-cluster extraction using a Segmentation, Detection, and Cluster-Extraction algorithm. It offers high defect-extraction accuracy, without any significant increase in test time and cost.

Defect cluster recognition system for fabricated semiconductor wafers

The International Technology Roadmap for Semiconductors (ITRS) identifies production test data as an essential element in improving design and technology in the manufacturing process feedback loop. One of the observations made from the high-volume production test data is that dies that fail due to a systematic failure have a tendency to form certain unique patterns that manifest as defect clusters at the wafer level. Identifying and categorising such clusters is a crucial step towards manufacturing yield improvement and implementation of real-time statistical process control. Addressing the semiconductor industrys needs, this research proposes an automatic defect cluster recognition system for semiconductor wafers that achieves up to 95% accuracy (depending on the product type).

Fast and Accurate Automatic Defect CLuster Extraction for Semiconductor Wafers

Reduction in integrated circuit (IC) half technology, which will no longer be sustainable by traditional fault isolation and failure analysis techniques. There is an urgent need for diagnostic software tools with (which manifest as clusters) observed from manufacturing defects can be traced back to a specific process, equipment or technology, a novel data mining algorithm defects from test data logs. This algorithm and provides accurate detection of 99%.

Evaluating the Performance of Different Classification Algorithms for Fabricated Semiconductor Wafers

Defect detection and classification is crucial in ensuring product quality and reliability. Classification provides information on problems related to the detected defects which can then be used to perform yield prediction, fault diagnosis, correcting manufacturing issues and process control. Accurate classification requires good selection of features to help distinguish between different cluster types. This research investigates the use of two features for classification: Polar Fourier Transform (PFT) and image Rotational Moment Invariant (RMI). It provides a comprehensive critical evaluation of several classification schemes in terms of performance and accuracy based on these features. It concludes by discussing the suitability of each classifier for classifying different types of defect clusters on fabricated semiconductor wafers.

Automatic Defect Cluster Extraction for Semiconductor Wafers

Defects on fabricated semiconductor wafers tend to cluster in distinguishable patterns. The ability to accurately identify these patterns allows manufacturers to trace their root causes to a specific process step or equipment. This paper deals with an algorithm that automatically extracts defect clusters. The algorithm performs cluster segmentation and detection by employing two separate and parallel processes. This increases robustness while maintaining high accuracy and speed of data processing. In this paper a new method that allows users to select a tradeoff threshold point between the acceptable false alarm and false rejection rates to suit their applications is introduced.

Towards identification of latent defects: Yield mining using defect characteristic model and clustering

Statistical yield modeling is used to calculate the probability of a die containing a latent defect based on its spatial relationship with other dies in its surrounding neighborhood. Previous research implements a blanket application of predictive yield mining on devices and assumes that a spatial relationship exists between killer defects screened at probe test, and latent defects screened at packaged level burn-in. This research investigates the use of the defect characteristic models as yield models to screen latent defects while taking into account wafers with defect clusters. It goes on to evaluate the pre-selected yield models in economic terms and interprets the results as either a predictive or descriptive yield model to describe and identify latent defects.

Structured database standardization framework for data mining of semiconductor manufacturing data

Semiconductor manufacturing is a very complex and sophisticated process and semiconductor manufacturing data are generally huge. In order to perform knowledge discovery from these huge sets of data, data has to be reduced in dimensions by only selecting certain fields which are of value towards a particular research. Most research is geared towards data mining and less importance is generally given to stages before data mining, namely problem definition, selection addition, preprocessing and data cleaning and transformation. This is undesirable because ad-hoc approaches to standardize the data during these initial stages tend to be inaccurate, any will affect the integrity of data mining performed in later stages. This paper proposes a structured data standardization framework which effectively breaks down huge semiconductor data of high dimensions into smaller values in order to perform knowledge discovery. The framework was effectively applied on two devices as a case study and the resulting processed data was successfully used for yield mining and defect clustering purposes.

Predictive Die-Level Reliability-Yield Modeling for Deep Sub-micron Devices

An increasing number of integrated circuits are going into the automotive sector where requirements on dependability are very high. As a result, there is a strong push in the semiconductor industry for achieving higher reliability standards while maintaining (or even lowering) the associated cost. Lately two efficient approaches to increase the effectiveness of reliability testing (including burn-in) have emerged. The first involves additional reliability test insertions. It is quite effective but limited to specific technology and processes. A more robust approach is to screen out devices with latent defects at probe (wafer level) through appropriate selection criteria before devices reach burn-in at the package- level. Traditional six-sigma quality assurance procedures are inadequate in coping with the fabrication process variations because the process is not static. Dynamic parts average testing (PAT) has been introduced by the Automotive Electronics Council to identify abnormal parts from a large population mean. It is the first standard procedure that deviates from the traditional six-sigma approach. Independent studies by Intel and IBM have shown that a die-level reliability predictor can screen unreliable devices better than dynamic PAT (which is based on a lot-level methodology). However, the die-level predictive model is relatively new and thus it needs further investigation to prove its usability in different technology and process settings. This paper studies the die-level predictive model for a specific wafer fabrication technology and critically assesses its performance and feasibility for implementation in a real-world production testing.

Critical assessment of die level predictor models

The reliability of integrated circuits is becoming of great importance lately as an increasing number of integrated circuits are being used in the automotive sector. As a result, the semiconductor industry is experiencing a greater demand to produce a higher reliability standard of devices without increasing the production cost. There are currently two approaches to increase the reliability of integrated circuits. The first implies new and improved methods of testing. The current reliability testing, which is the Burn-In test, is an expensive process; this provokes the need to further develop and enhance the second approach. The second approach is to predict the lifespan of a device at wafer level. Several prediction models are applied to investigate the correlation between the probe level yield and the burn-in yield. Through this approach, devices which have short lifespan would then be discarded before packaging. There are few prediction models proposed, but those models are static and do not accommodate the variation introduced through the fabrication processes. Though studies have shown that there are correlation between probe level yield and Burn-In yield, the correlation obtained is not significant enough. Therefore, further classification process is applied to wafers having distinct reliability characteristics, before the prediction models are applied. This will in turn optimize the correlation.

Identifying Systematic Failures on Semiconductor Wafers Using ADCAS

Product engineers are often called upon to use their unique mix of expertise and intuition to solve yield puzzles. Any tool that can help ease and automate the process is a welcome one. Industrial case studies demonstrate a new tools potential to provide automatically accurate, and potentially early, indications of underlying root cause for low-yielding wafers.