Chris Dick

Polynomial-transform-based approach to computing 2D DFTs using reconfigurable computers

Considerable success has been achieved in developing signal processing algorithms that are efficient from the standpoint of number of operations. However, what is needed now is to develop new algorithms which are better adapted to existing hardware, or to device new architectures that more efficiently exploit existing signal processing algorithms. This latter approach forms the basis of this paper. An FPGA architecture is described that takes advantage of the reduced computational requirements of the polynomial transform method for computing 2-D DFTs. The performance of the architecture is presented and is shown to use 36% less FPGA resources than a row-column DFT processor. A multi-FPGA architecture is described that is capable of processing 24 512 by 512 pixel images per second. The multi-FPGA processor is 46% more area efficient than a row-column DFT implementation.

On the re-quantization of data to implement high-order narrow-band filters using reconfigurable logic

This paper addresses the problem of implementing narrow-band FIR filters using FPGAs. A method based on re-quantization of the input data stream using a sigma-delta modulator is presented. The reduced bit length representation of the re-quantized input samples removes the requirement for a full multiplier in the filter hardware. The filtering technique is described and implementation results using a Xilinx XC4010 FPGA are presented. Using a bit-serial approach, a 100 tap narrow-band filter operating at a sample rate of 1.56 MHz has been developed. A 20 tap bit-parallel filter can be accommodated in one XC4010PG191-4 and operates at a sample rate of 22.6 MHz.

The scalability of linear filters on hypercube concurrent computers

The general concept in solving a problem on a parallel machine requires subdividing a large problem into processes, each of which can be computed on a single processor. This can be a formidable task requiring substantial communication and control overhead. It is easy to speculate what may happen when one implements various applications on such a system. But nothing teaches one as surely as actually implementing real problems with real software on real hardware. This paper reports on the implementation and performance of a hypercube arrangement of VLSI DSP processors (TMS320C30) for FIR filtering. Two approaches are considered. A direct partitioning of the standard FIR filter structure and a decomposition of the fast FIR algorithm described by Mou and Duhamel (1987). Two interprocessor communication strategies are described. Models constructed from measurements on a prototype machine are used to calculate the performance of filters on higher dimensional hypercubes.<<ETX>>