Chris Dick

Computing the Discrete Fourier Transform on FPGA Based Systolic Arrays

Reconfigurable logic arrays allow for the creation on the one physical hardware platform many different virtual circuits. A configuration bit-stream loaded into the logic array specifies the virtual circuit implemented. This paper addresses the problem of implementing FFTs using virtual computers based on Xilinx FPGAs. A systolic array processor architecture consisting of processing elements (PEs) employing CORDIC arithmetic is presented. The CORDIC approach removes the requirement for area consuming multipliers in the design. The method is suitable for handling power-of-2 and non power-of-2 transform lengths. The modular nature of the design provides for a highly scalable architecture that provides the system designer with a flexible mechanism for making cost-performance tradeoffs. The array processor and PE architecture are described. Based on simulation results, FPGA device utilization and transform execution time are calculated.

Virtual signal processors

Abstract The introduction of SRAM-based field programmable gate arrays (FPGAs) has opened up a new dimension to parallel computing architectures. This paper describes an alternative approach to parallel computing — reconfigurable or virtual parallel processing (VPP). Rather than mapping an application onto a given parallel machine, the WP approach synthesizes the appropriate type and number of processing elements, as well as the interconnection topology, that is optimal for the application. For each application, configuration data is downloaded to the machine that personalizes the hardware for the task at hand. The paper provides a brief description of the authors reconfigurable computer, Archimedes . The benefits of the VPP approach are highlighted by two example applications — the 2-D FFT and a narrow-band digital filter. A novel parallel implementation of a polynomial transform based 2-D transform is described and compared with results for distributed memory parallel machines that have been reported in the literature. The comparison highlights the computational advantage provided by reconfigurable computing. The digital filter implementation employs sigma–delta modulation encoding to reduce the arithmetic workload. The application of this technology to a communications receiver is explained.

Narrow-band FIR filtering with FPGAs using sigma-delta modulation encoding

This paper addresses the problem of implementing narrow-band FIR filters using FPGAs. Rather than employing a conventional multiply-accumulate unit to compute the inner-product, an alternative method based on re-quantization of the input data stream using a sigma-delta modulator is presented. The re-quantization process preserves the dynamic range of the signal components contained in the bandwidth of the filter, while shifting the re-quantization noise to the spectral region to be rejected by the filter. The reduced bit length representation of the re-quantized input data samples removes the requirment for a full multiplier in the filter hardware. This makes the method very attractive for realization using FPGA technology. The filtering technique is described and implementation results using a Xilinx XC4010 FPGA are presented. A 200-tap filter implemented in a single FPGA achieves a computation rate of 415 MOPS and has a memory bandwidth of 1.66 Gbytes/s. An extension of the method using a quadrature re-quantizer and filter is also presented.

FPGA based systolic array architectures for computing the discrete Fourier transform

Reconfigurable logic arrays allow for the creation on the one physical hardware platform many different virtual circuits. A configuration bit-stream loaded into the logic array specifies the virtual circuit implemented. This paper addresses the problem of implementing FFTs using custom computing machines based on Xilinx FPGAs. A systolic array processor architecture consisting of processing elements (PEs) employing CORDIC arithmetic is presented. The CORDIC approach removes the requirement for area consuming multipliers in the design. The method is suitable for handling power-of-2 and non power-of-2 transform lengths. The modular nature of the design provides for a highly scalable architecture that gives the system designer a flexible mechanism for making cost-performance tradeoffs. The array processor and PE architecture are described. Based on simulation results, FPGA device utilization and transform execution times are calculated.

Fir Filtering with Fpgas Using Quadrature Sigma-Delta Modulation Encoding

This paper addresses the problem of implementing narrow-band FIR filters using FPGAs. The method uses a tunable quadrature sigma-delta modulator to re-quantise a real- or complex-valued input stream to a reduced precision, so removing the requirement for a full multiplier in the filter hardware. This makes the technique very attractive for implementation using FPGAs. The re-quantisation process preserves the dynamic range of the signal components contained in the bandwidth of the filter, while shifting the re-quantisation noise to the spectral region to be rejected by the filter. The filter architecture described and its implementation using Xilinx FPGAs is presented.

Computing 2-D DFTs Using FPGAs

Considerable success has been achieved in developing signal processing algorithms that are efficient from the standpoint of number of operations. However, what is needed now is to develop new algorithms which are better adapted to existing hardware, or to devise new architectures that more efficiently exploit existing signal processing algorithms. This latter approach forms the basis of this paper. An FPGA architecture is described that takes advantage of the reduced computational requirements of the polynomial transform method for computing 2-D DFTs. The performance of the architecture is presented and is shown to use 31% less FPGA resources than a row-column DFT processor. A multi-FPGA architecture is described that is capable of processing 24 512 × 512-pixel images per second. The multi-FPGA processor is 38% more area efficient than a row-column DFT implementation.

Implementing narrow-band FIR filters using FPGAs

This paper addresses the problem of implementing narrow-band FIR filters using FPGAs. A method based on re-quantization of the input data stream using a sigma-delta modulator is presented. The reduced bit length representation of the re-quantized input samples removes the requirement for a full multiplier in the filter hardware. The filtering technique is described and implementation results using a Xilinx XC4010 FPGA are presented. Using a bit-serial approach, a 200 tap narrow-band filter operating at a sample rate of 1.56 MHz has been developed.

Reconfigurable gate array architectures for real time digital signal processing

The number of usable gates in field programmable gate array (FPGA) logic has recently reached a level which allows their use as computational structures in digital signal processing (DSP) applications. This paper reports on the development of a scalable computing architecture based on Xilinx (CMOS) XC4010 FPGAs for real-time digital signal processing. The architecture requirements for efficient implementation of common DSP algorithms on FPGA platforms are considered. An analysis of the implementation and performance of a high-bandwidth finite impulse response (FIR) filter is presented. A second design using data requantization and spectral shaping to achieve higher order filters is also described.<<ETX>>

Virtual parallel processors

The introduction of SRAM-based field programmable gate arrays (FPGAs) has opened-up a new dimension to parallel computing architectures. This paper describes an alternative approach to parallel computing-reconfigurable or virtual parallel processing (VPP). Rather than mapping an application onto a given parallel machine, the VPP approach synthesizes the appropriate type and number of processing elements, as well as the interconnection topology, that is optimal for the application. For each application, configuration data is downloaded to the machine that personalizes the hardware for the task at hand. The paper provides a brief description of the authors reconfigurable computer, Archimedes. The benefits of the VPP approach are highlighted by an example application-the 2-D FFT. A novel parallel implementation of a polynomial transform based 2-D transform is described and compared to results for distributed memory parallel machines that have been reported in the literature. The comparison highlights the computational advantage provided by reconfigurable computing.

FPGA implementation of high-order FIR filters by requantizing the input data stream

This paper addresses the problem of implementing narrow-band FIR filters using FPGAa. Rather than employing a conventional multiply-accumulate unit to compute the inner-product, an alternative method based on requantization of the input data stream is presented. The requantization process preserves the dynamic range of the signal components contained in the bandwidth of the filter, while shifting the requantization noise to the spectral region to be rejected by the filter. The reduced bit length representation of the requantization input data samples removes the requirement for a full multiplier in the filter hardware. This makes the method very attractive for realization using FPGA technology. The filtering technique is described, and implementation results using a Xilinx XC4010 FPGA are presented.