Chris M. Corbet

Field Effect Transistors with Current Saturation and Voltage Gain in Ultrathin ReS2

We report the fabrication and device characteristics of exfoliated, few-layer, dual-gated ReS2 field effect transistors (FETs). The ReS2 FETs display n-type behavior with a room temperature Ion/I(off) of 10(5). Many devices were studied with a maximum intrinsic mobility of 12 cm(2) · V(-1) · s(-1) at room temperature and 26 cm(2) · V(-1) · s(-1) at 77 K. The Cr/Au-ReS2 contact resistance determined using the transfer length method is gate-bias dependent and ranges from 175 kΩ · μm to 5 kΩ · μm, and shows an exponential dependence on back-gate voltage indicating Schottky barriers at the source and drain contacts. Dual-gated ReS2 FETs demonstrate current saturation, voltage gain, and a subthreshold swing of 148 mV/decade.

CMOS-compatible synthesis of large-area, high-mobility graphene by chemical vapor deposition of acetylene on cobalt thin films.

We demonstrate the synthesis of large-area graphene on Co, a complementary metal-oxide-semiconductor (CMOS)-compatible metal, using acetylene (C(2)H(2)) as a precursor in a chemical vapor deposition (CVD)-based method. Cobalt films were deposited on SiO(2)/Si, and the influence of Co film thickness on monolayer graphene growth was studied, based on the solubility of C in Co. The surface area coverage of monolayer graphene was observed to increase with decreasing Co film thickness. A thorough Raman spectroscopic analysis reveals that graphene films, grown on an optimized Co film thickness, are principally composed of monolayer graphene. Transport properties of monolayer graphene films were investigated by fabrication of back-gated graphene field-effect transistors (GFETs), which exhibited high hole and electron mobility of ∼1600 cm(2)/V s and ∼1000 cm(2)/V s, respectively, and a low trap density of ∼1.2 × 10(11) cm(-2).

Scaling of Al2O3 dielectric for graphene field-effect transistors

We investigate the scaling of Al2O3 dielectric on graphene by atomic layer deposition (ALD) using ultra-thin, oxidized Ti and Al films as nucleation layers. We show that the nucleation layer significantly impacts the dielectric constant (k) and morphology of the ALD Al2O3, yielding k = 5.5 and k = 12.7 for Al and Ti nucleation layers, respectively. Transmission electron microscopy shows that Al2O3 grown using the Ti interface is partially crystalline, while Al2O3 grown on Al is amorphous. Using a spatially uniform 0.6 nm-thick Ti nucleation layer, we demonstrate graphene field-effect transistors with top dielectric stacks as thin as 2.6 nm.

van der Waals Heterostructures with High Accuracy Rotational Alignment

We describe the realization of van der Waals (vdW) heterostructures with accurate rotational alignment of individual layer crystal axes. We illustrate the approach by demonstrating a Bernal-stacked bilayer graphene formed using successive transfers of monolayer graphene flakes. The Raman spectra of this artificial bilayer graphene possess a wide 2D band, which is best fit by four Lorentzians, consistent with Bernal stacking. Scanning tunneling microscopy reveals no moiré pattern on the artificial bilayer graphene, and tunneling spectroscopy as a function of gate voltage reveals a constant density of states, also in agreement with Bernal stacking. In addition, electron transport probed in dual-gated samples reveals a band gap opening as a function of transverse electric field. To illustrate the applicability of this technique to realize vdW heterostructuctures in which the functionality is critically dependent on rotational alignment, we demonstrate resonant tunneling double bilayer graphene heterostructures separated by hexagonal boron-nitride dielectric.

Band Alignment in WSe2–Graphene Heterostructures

Using different types of WSe2 and graphene-based heterostructures, we experimentally determine the offset between the graphene neutrality point and the WSe2 conduction and valence band edges, as well as the WSe2 dielectric constant along the c-axis. In a first heterostructure, consisting of WSe2-on-graphene, we use the WSe2 layer as the top dielectric in dual-gated graphene field-effect transistors to determine the WSe2 capacitance as a function of thickness, and the WSe2 dielectric constant along the c-axis. In a second heterostructure consisting of graphene-on-WSe2, the lateral electron transport shows ambipolar behavior characteristic of graphene combined with a conductivity saturation at sufficiently high positive (negative) gate bias, associated with carrier population of the conduction (valence) band in WSe2. By combining the experimental results from both heterostructures, we determine the band offset between the graphene charge neutrality point, and the WSe2 conduction and valence band edges.

Bilayer Graphene-Hexagonal Boron Nitride Heterostructure Negative Differential Resistance Interlayer Tunnel FET

We present the room temperature operation of a vertical tunneling field-effect transistor using a stacked double bilayer graphene (BLG) and hexagonal boron nitride heterostructure. The device shows two tunneling resonances with negative differential resistance (NDR). An analysis of the electrostatic potential drop across the heterostructure indicates the resonances are associated with the relative alignment of the lower or upper bands of the two BLG. Using the NDR characteristic of the device, one-transistor latch or SRAM operation is demonstrated. The device characteristics are largely insensitive to temperature from 1.5 to 300 K.

Self-aligned graphene field-effect transistors with polyethyleneimine doped source/drain access regions

We report a method of fabricating self-aligned, top-gated graphene field-effect transistors (GFETs) employing polyethyleneimine spin-on-doped source/drain access regions, resulting in a 2X reduction of access resistance and a 2.5X improvement in device electrical characteristics, over undoped devices. The GFETs on Si/SiO2 substrates have high carrier mobilities of up to 6300 cm2/Vs. Self-aligned spin-on-doping is applicable to GFETs on arbitrary substrates, as demonstrated by a 3X enhancement in performance for GFETs on insulating quartz substrates, which are better suited for radio frequency applications.

Improved contact resistance in ReSe2 thin film field-effect transistors

We report the fabrication and device characteristics of exfoliated, few-layer, ReSe2 field effect transistors (FET) and a method to improve contact resistance by up to three orders of magnitude using ultra-high-vacuum annealing (UHV). Many devices were studied in the absence of light and we found an average contact of 750 Ω · cm after UHV treatment. The median FET metrics were similar to other transition metal dichalcogenides: field effect mobility ∼6.7 cm2/V · s, subthreshold swing ∼1.2 V/decade, and Ion/Ioff ∼ 105. In devices with low Rc current saturation was observed and is attributed to injection limited transport.

Oxidized titanium as a gate dielectric for graphene field effect transistors and its tunneling mechanisms.

We fabricate and characterize a set of dual-gated graphene field effect transistors using a novel physical vapor deposition technique in which titanium is evaporated onto the graphene channel in 10 Å cycles and oxidized in ambient to form a top-gate dielectric. A combination of X-ray photoemission spectroscopy, ellipsometry, and transmission electron microscopy suggests that the titanium is oxidizing in situ to titanium dioxide. Electrical characterization of our devices yields a dielectric constant of κ = 6.9 with final mobilities above 5500 cm(2)/(V s). Low temperature analysis of the gate-leakage current in the devices gives a potential barrier of 0.78 eV in the conduction band and a trap depth of 45 meV below the conduction band.

Gate capacitance scaling and graphene field-effect transistors with ultra-thin top-gate dielectrics

Graphene has emerged recently as an attractive channel material for high frequency analog device applications. High carrier mobility and large gate capacitance are both desirable attributes for such devices. A main obstacle however in depositing thin dielectrics on graphene, with high dielectric constant is its chemical inertness. This obstacle can be overcome by either directly depositing the dielectric, e.g. using sputtering or e-beam evaporation, or by using a seed layer which provides nucleation sites for atomic layer deposition (ALD). The interfacial layer however reduces the gate capacitance and can also impact the quality of the ALD dielectric subsequently grown. Here we provide a systematic study of gate capacitance scaling of graphene field effect transistors with Al2O3 gate dielectric with two seed layers, oxidized aluminum and oxidized titanium. Our results show the oxidized Ti film on graphene provides a smooth surface, which allows us to use a Ti nucleation layer as thin as 6Å, and achieve uniform coverage required for the subsequent ALD. The k-value of the ALD Al2O3 grown on graphene using oxidized Ti as nucleation layer is 12.7, a value 2.5 times larger than the ALD Al2O3 grown using oxidized Al. We demonstrate graphene devices with ultra-thin top gate dielectrics, with EOT values as low as 3.5 nm.