Chris Winstead

CMOS analog MAP decoder for (8,4) Hamming code

Design and test results for a fully integrated translinear tail-biting MAP error-control decoder are presented. Decoder designs have been reported for various applications which make use of analog computation, mostly for Viterbi-style decoders. MAP decoders are more complex, and are necessary components of powerful iterative decoding systems such as turbo codes. Analog circuits may require less area and power than digital implementations in high-speed iterative applications. Our (8, 4) Hamming decoder, implemented in an AMI 0.5-/spl mu/m process, is the first functioning CMOS analog MAP decoder. While designed to operate in subthreshold, the decoder also functions above threshold with a small performance penalty. The chip has been tested at bit rates up to 2 Mb/s, and simulations indicate a top speed of about 10 Mb/s in strong inversion. The decoder circuit size is 0.82 mm/sup 2/, and typical power consumption is 1 mW at 1 Mb/s.

Stochastic iterative decoders

This paper presents a stochastic algorithm for iterative error control decoding. We show that the stochastic decoding algorithm is an approximation of the sum-product algorithm. When the codes factor graph is a tree, as with trellises, the algorithm approaches maximum a-posteriori decoding. We also demonstrate a stochastic approximations to the alternative update rule successive relaxation. Stochastic decoders have very simple digital implementations which have almost no RAM requirements. We present example stochastic decoders for a trellis-based Hamming code, and for a block turbo code constructed from Hamming codes

Low-voltage CMOS circuits for analog iterative decoders

Iterative decoders, including Turbo decoders, provide near-optimal error protection for various communication channels and storage media. CMOS analog implementations of these decoders offer dramatic savings in complexity and power consumption, compared to digital architectures. Conventional CMOS analog decoders must have supply voltage greater than 1 V. A new low-voltage architecture is proposed which reduces the required supply voltage by at least 0.4 V. It is shown that the low-voltage architecture can be used to implement the general sum-product algorithm. The low-voltage analog architecture is then useful for implementing Turbo and low-density parity check decoders. The low-voltage architecture introduces new requirements for signal normalization, which are discussed. Measured results for two fabricated low-voltage analog decoders are also presented.

Noisy Gradient Descent Bit-Flip Decoding for LDPC Codes

A modified Gradient Descent Bit Flipping (GDBF) algorithm is proposed for decoding Low Density Parity Check (LDPC) codes on the binary-input additive white Gaussian noise channel. The new algorithm, called Noisy GDBF (NGDBF), introduces a random perturbation into each symbol metric at each iteration. The noise perturbation allows the algorithm to escape from undesirable local maxima, resulting in improved performance. A combination of heuristic improvements to the algorithm are proposed and evaluated. When the proposed heuristics are applied, NGDBF performs better than any previously reported GDBF variant, and comes within 0.5 dB of the belief propagation algorithm for several tested codes. Unlike other previous GDBF algorithms that provide an escape from local maxima, the proposed algorithm uses only local, fully parallelizable operations and does not require computing a global objective function or a sort over symbol metrics, making it highly efficient in comparison. The proposed NGDBF algorithm requires channel state information which must be obtained from a signal to noise ratio (SNR) estimator. Architectural details are presented for implementing the NGDBF algorithm. Complexity analysis and optimizations are also discussed.

A Probabilistic LDPC-Coded Fault Compensation Technique for Reliable Nanoscale Computing

A method is proposed for computing with unreliable nanoscale devices that have a high rate of transient errors. Errors are corrected using a probabilistic circuit in which device noise is leveraged as a computational asset. Example designs that achieve a low output bit error probability are presented. The effect of permanent defects is also evaluated, and transient device noise is found to be beneficial for correcting hard defects for defect rates of as high as 0.1% and transient fault rates above 1%. When compared with existing fault-tolerant methods, the sample design requires considerably fewer redundant gates to achieve reliable operation. These results predict that some degree of engineered randomness may prove to be a useful signal-processing feature in future nanoelectronic systems.

Design and Test of Genetic Circuits Using iBioSim

The simulation of biological systems prior to their physical implementation can save time, money, and potentially provide insights into alternate designs. This paper presents a simulation environment which allows for a visual design process ultimately leading to a formal model which can be efficiently simulated.

Analog soft decoding for multi-level memories

This paper proposes analog soft-information decoding circuits for error protection in multi-level memories, providing stronger error protection than binary error-correcting codes. The cell capacitance can then be reduced without an increase in the soft error rate. Analog decoders perform soft-information decoding with very low area requirements. We introduce a multi-level analog interface circuit for analog decoding of MLDRAM signals. We also apply basic information theory to reveal the possibilities and limitations of coding in multi-level memories.

CPS: an efficiency-motivated attack against autonomous vehicular transportation

This work describes a new type of efficiency attack that can be used to degrade the performance of automated vehicular transportation systems. Next-generation transportation technologies will leverage increasing use of vehicle automation. Proposed vehicular automation systems include cooperative adaptive cruise control and vehicle platooning strategies which require cooperation and coordination among vehicles. These strategies are intended to optimize through-put and energy usage in future highway systems, but, as we demonstrate, they also introduce new vulnerabilities. In this work we show that a typical platooning system would allow a maliciously controlled vehicle to exert subtle influence on the motion of surrounding vehicles. This effect can be used to increase the energy expenditure of surrounding vehicles by 20% to 300%.

Relaxation Dynamics in Stochastic Iterative Decoders

Stochastic decoding is a recently proposed approach for graph-based iterative error control decoding. We present and investigate three hysteresis methods for stochastic decoding on graphs with cycles and show their close relationship with the successive relaxation method. Implementation results demonstrate the tradeoff in bit error rate performance with circuit complexity.

Utilizing stochastic model checking to analyze genetic circuits

When designing and analyzing genetic circuits, researchers are often interested in the probability of the system reaching a given state within a certain amount of time. Usually, this involves simulating the system to produce some time series data and analyzing this data to discern the state probabilities. However, as the complexity of models of genetic circuits grow, it becomes more difficult for researchers to reason about the different states by looking only at time series simulation results of the models. To address this problem, this paper employs the use of stochastic model checking, a method for determining the likelihood that certain events occur in a system, with continuous stochastic logic (CSL) properties to obtain similar results. This goal is accomplished by the introduction of a methodology for converting a genetic circuit model (GCM) into a continuous-time Markov chain (CTMC). This CTMC is analyzed using transient Markov chain analysis to determine the likelihood that the circuit satisfies a given CSL property in a finite amount of time. This paper illustrates a use of this methodology to determine the likelihood of failure in a genetic toggle switch and compares these results to stochastic simulation-based analysis of this same circuit. Our results show that this method results in a substantial speedup as compared with conventional simulation-based approaches.