Christian Hafer

Code reorganization for instruction caches

Conventional cache optimizations are usually confined to hardware. However, software optimizations are more flexible and allow faster hardware due to reduced complexity. The authors describe a method of using direct mapped caches more effectively by adapting program behavior. They introduce coarse-grained code reorganization as a software method of improving instruction cache hit rates. Based on trace analysis, cache conflicts are computed taking into account both temporal and spatial program locality. This leads to a precise prediction of cache behavior which is used to reorganize the code in address space. The potential of the solution is demonstrated by applying the code reorganizer to a variety of SPEC benchmarks. Both simulated and measured results are presented for various cache sizes. The results show significant performance gains across the various SPEC programs evaluated.<<ETX>>

Improving performance by cache driven memory management

The efficient utilization of caches is crucial for a competitive memory hierarchy. Access times required by modern processors are continuously decreasing. Direct mapped caches provide the shortest access time. Using them yields reduced hardware costs and fast memory access but implies additional misses in the cache, resulting in performance degradation. Another source of conflicts is the addressing scheme if caches are physically addressed. For such caches, memory management affects cache utilization. Enhancements in virtual memory management as presented in this paper reduce cache misses by as much as 80% for real-indexed caches. We developed three algorithms that use runtime information. All of them are suitable for direct-mapped and set associative caches. Applied to SPECint92 benchmark suite, we measured a performance improvement of 6.9% in a multiprogramming environment for a R4000 based UNIX workstation. This figure also includes the overhead caused by the more complex memory management.<<ETX>>

Balanced Systems: A New Approach to Integrate Hardware and Software Design

The runtime gain to be obtained by integrating hardware and software design is substantial. E.g. in memory hierarchies, in particular in caches, performance increases of typically 20% could be observed for a wide selection of workloads. These performance increases have been acquired in a first step without using knowledge about program behavior. Higher benefits can be expected for a specifically designed algorithm.

COLIBRI: A Coprocessor for LISP based on RISC

Traditional LISP machines are based on processors with complex microcoded instruction sets. Those processors require enormous efforts in both hardware and software design to achieve high LISP performance.