Christian Le

RAPL: memory power estimation and capping

The drive for higher performance and energy efficiency in data-centers has influenced trends toward increased power and cooling requirements in the facilities. Since enterprise servers rarely operate at their peak capacity, efficient power capping is deemed as a critical component of modern enterprise computing environments. In this paper we propose a new power measurement and power limiting architecture for main memory. Specifically, we describe a new approach for measuring memory power and demonstrate its applicability to a novel power limiting algorithm. We implement and evaluate our approach in the modern servers and show that we achieve up to 40% lower performance impact when compared to the state-of-art baseline across the power limiting range.

Unified extensible firmware interface: An innovative approach to DRAM power control

As computing becomes more pervasive across an ever-increasing array of devices and as more complex solutions are integrated in silicon, the role of intelligent firmware is becoming ever more critical for enabling and unleashing advanced platform capabilities. Furthermore, since enterprise servers rarely operate at their peak capacity, efficient power capping is deemed as a critical component of modern enterprise computing environments. In this paper we present the role of platform firmware in DRAM power estimation, optimization and control. We develop firmware assisted smarts that optimizes the DRAM locality as well as enhances the accuracy of the DRAM power limiting (RAPL).

Autonomic tool for optimal cache-sharing using evolutionary techniques

Chip multiprocessors are subject to performance degradation due to inefficient cache management. Conventional cache distribution schemes treat all cores equally, leading to cache-contention issues caused by thrashing behaviors. This paper presents an automation tool that ensures optimal cache-sharing amongst cores executing workloads concurrently and competing for cache resources. We demonstrate that dynamic cache partitioning among selected cores improves overall performance. Our automation tool uses CPU performance counters that feed into a genetic algorithm to ensure optimal cache distribution. This scheme minimizes the overall LLC miss rate by 12.879% and increases the overall IPC by 2.426% over the conventional cache partitioning.

Dynamic energy allocation for coordinated optimization in enterprise workloads

Power optimization and power control are challenging issues for server computer systems. To obtain power optimization in an enterprise server, one needs to observe temporal behavior of workloads, and how they contribute to relative variations in power drawn by different server components. This depth of analysis helps to validate and quantify various energy/performance trends important for power modeling. In this paper we discuss an adaptive infrastructure to synthesize models that dynamically estimate the throughput and latency characteristics based on component level power distribution in a server. In this infrastructure, we capture telemetry data from a distributed set of physical and logical sensors in the system and use it to train models for various phases of the workload. Once trained, system power, throughput and latency models participate in an optimization heuristics that re-distribute the power to maximize the overall performance/watt of an enterprise server. We demonstrate modeling accuracy and improvement in energy efficiency due to coordinated power allocation among server components.

Unified extensible firmware interface: An innovative infrastructure for power/thermal autonomics

As computing becomes more pervasive across an ever-increasing array of devices and as more complex solutions are integrated in silicon, the role of intelligent firmware is becoming ever more critical for enabling and unleashing advanced platform capabilities. In this paper we present platform power/thermal autonomics function as an OS independent EFI client that interacts with the power and thermal sensors within a system that can stress the system, provide data-telemetry channel, regress and synthesize the power/performance equations in a controlled environment.

A novel approach to memory power estimation using machine learning

Reducing power consumption has become a priority in microprocessor design as more devices become mobile and as the density and speed of components lead to power dissipation issues. Power allocation strategies for individual components within a chip are being researched to determine optimal configurations to balance power and performance. Modelling and estimation tools are necessary in order to understand the behaviour of energy consumption in a run time environment. This paper discusses a novel approach to power metering by estimating it using a set of observed variables that share a linear or non-linear correlation to the power consumption. The machine learning approaches exploit the statistical relationship among potential variables and power consumption. We show that Support Vector Machine regression (SVR), Genetic Algorithms (GA) and Neural Networks (NN) can all be used to cheaply and easily predict memory power usage based on these observed variables.