Christian Menolfi

A low-noise CMOS instrumentation amplifier for thermoelectric infrared detectors

A low-noise CMOS instrumentation amplifier for low-frequency thermoelectric infrared sensor applications is described which uses a chopper technique to reduce low-frequency noise and offset. The offset reduction efficiency of the band-pass filter, implemented to reduce residual offset due to clock feedthrough, has been analyzed and experimentally verified. The circuit has been integrated in a transistor-only 1-/spl mu/m single-poly n-well CMOS process. It features a gain of 52 dB with a 500 Hz bandwidth and a common-mode rejection ratio (CMRR) of more than 70 dB. The equivalent input low frequency noise is 15 nV//spl radic/Hz. The typical residual input offset is 1.5 /spl mu/V. The amplifier power consumption is 1.3 mW.

A fully integrated, untrimmed CMOS instrumentation amplifier with submicrovolt offset

A low-noise CMOS instrumentation amplifier intended for low-frequency thermoelectric microsensor applications is presented that achieves submicrovolt offset and noise. Key to its performance is the chopper modulation technique combined with a bandpass filter and a matching on-chip oscillator. No external components or trimming are required. The achievable offset performance depends on the bandpass filter Q and the oscillator-to-bandpass filter matching accuracy. Constraints are derived for an optimum Q and a given matching accuracy. The improvement of common-mode rejection ratio (CMRR) in chopper amplifiers is discussed. The amplifier features a total gain of 77/spl plusmn/0.3 dB and a bandwidth of approximately 600 Hz. The measured low-frequency input noise is 8.5 nV//spl radic/Hz and the input offset is 600 nV. The measured low-frequency CMRR is better than 150 dB. The circuit has been implemented in a standard 1-/spl mu/m single-poly CMOS process.

A 25-Gb/s CDR in 90-nm CMOS for High-Density Interconnects

This paper presents a clock-and-data recovery (CDR) for pseudo-synchronous high-density link applications. The CDR is a first-order bang-bang (BB) topology implemented in a standard CMOS process and consists of a phase interpolator, a linear half-rate phase detector, an analog filter followed by a limiter and a digital loop filter operating at a reduced clock rate. A detailed BB CDR analysis derives the maximum tracking range, slew-rate limited jitter tolerance and maximum loop delay. The circuit is optimized for high speed as well as low area and power consumption. The CDR operates from 8-28 Gb/s at a BER of <10-12 and tracks frequency deviations between the incoming data and the reference clock of up to plusmn122 ppm. The sinusoidal jitter tolerance is >0.35UIpp for jitter frequencies les100 MHz and the total timing jitter of the recovered half-rate output data amounts to 0.22 UIpp at a BER=10-12. The core CDR circuit occupies a chip area of 0.07 mm2 and consumes 98 mW from a 1.1-V supply

A 25Gb/s CDR in 90nm CMOS for High-Density Interconnects

A CDR for source-synchronous high-density link applications receives 25Gb/s at a BER of <10-12. The CDR is a first-order bang-bang topology employing a phase interpolator, linear half-rate phase detector, an analog filter followed by a limiter and a digital loop filter. The core CDR circuit occupies 0.09mm2 and consumes 98mW from a 1.1V supply

Low-complexity adaptive equalization for high-speed chip-to-chip communication paths by zero-forcing of jitter components

In this letter, we show how a prefilter can be automatically adapted to open the data eye in a nonreturn to zero transmission system using only two binary samples per bit. Although the equalizer primarily aims to minimize timing jitter with a zero-forcing criterion, this equalization method also results in nearly optimum vertical eye opening, thereby causing very little overhead in complexity and power consumption. The target application is low-power high-speed serial links to transfer data between chips over a printed circuit board

Temperature And Supply Voltage Stabilized Power Driver For Flow Sensors

Among the many integrated flow sensors that have been developed recently [l, 2 , 3 , 4 ] , those based on standard industrial CMOS processes have the advantage of lower cost and wider availability of foundries [4]. In addition, interface electronics can be more readily included on the same chip as the sensors, thus enhancing the latter’s performance and reducing the packaging complexity and pin-count. Using maskless EDP etching, thermopile based sensors can be realized as shown in Fig. 1, where polysilicon and aluminium are used to form thermocouples and polysilicon as heating resistor. In differential structures the flow velocity is proportional to the thermocouple’s Seebeck coefficient and the temperature diffence AT between the two thermopiles due to the convection of heat by the air flow to be measured. This AT not only depends on the rate of the air flow, but also on the heating power provided by the heating resistors. It is important that the heating power is independent to temperature and supply voltage variations to achieve good linearity for the flow sensor. This contribution describes a CMOS circuit that delivers stable power to heating resistors. Figure 1: Integrated flour s e n s o r s based o n thermopiles TEMPERATURE INDEPENDENT HEATING POWER It is well known that polysilicon have relatively high temperature coefficients of the order of 0.1%/K due to the temperature dependence of their mobility. If a constant voltage or a constant current is used to drive the heating resistor, the resulting heating power is (inversely) proportional to the resistance which is in turn dependent on temperature. This causes nonlinearity in the flow sensor readout. For a l0OK temperature range, the deviation is in the range of 10% which is too large in most applications. An effective way of reducing this heating power temperature dependence is to connect a series resistor of the same value as the heating resistor and drive the two resistors with a constant voltage [5], as shown in Fig. 2. If the compensation resistor Rc is kept ”cold” by a thermal ground, then it can be shown that the relative heating power deviation AP due to relative resistance change AR is given by A relative resistance change of 10% will now cause a heating power change of only 0.25% which is accurate enough for most applications. More elaborate schemes [6, 71 will hardly achieve better compensation in practice. Similarly, a ”cold” compensation resistor can be connected in parallel to the heating resistor when power is supplied by a constant current source. This is shown in Fig. 3. Both schemes in Fig. 2 and Fig. 3 have the drawback that only half the power is delivered to the heating resistor. Even if power consumption is of minor consideration the limitations of the transistors in active voltage and current sources will limit the power deliverable to the resistors for a given supply voltage. Losing half the power to the compensation resistor means halving the sensitivity of the flow sensor. For example to deliver 5mW to the heating resistor from a 5V supply requires 2mA through the current source in Fig. 3. At such a current it becomes increasingly difficult to keep the output resistance of the current TRANSDUCERS ‘95 . EUROSENSORS IX The 8th International Conference on Solid-state Sensors and Actuators, and Eurosensors IX. Stockholm, Sweden, June 25-29, 1995 440

CMOS ADCs Towards 100 GS/s and Beyond

The implementation of a 64x time-interleaved ADC in 32nm CMOS SOI is analyzed. Measurement results confirm 33 dB SNDR up to 19.9 GHz at 90 GS/s and 1.2V supply. Architecture details and analysis show insights into limitations and potentials of the chosen architecture. In par-ticular the input bandwidth is of concern for ADCs at more than 64 GS/s, as a larger number of sampling switches in-creases the parasitic load and reduces the input bandwidth. Insights on a simplified analysis of interleaver structures and existing solutions to bandwidth issues are highlighted and show a path to extend the sampling speed of CMOS ADCs beyond 100 GS/s.

A Low-Power 40 Gbit/s Receiver Circuit Based on Full-Swing CMOS-Style Clocking

We describe circuit techniques for a 40 Gbit/s CMOS CDR circuit in 65 nm CMOS-SOI technology, which mostly uses a full-swing CMOS circuit style to minimize power and area. The quarter rate receiver uses a phase-programmable PLL (P-PLL) architecture for clock generation and phase tracking, and implements a high-speed sampler based on CMOS SenseAmp latches. The circuit uses 0.03mm2 of chip area, and consumes 72mV of power at 40 Gbps data rate. We describe in detail the implementation of several crucial components, i.e. the ring VCO, which was optimized for high-speed operation, and the sampling and demultiplexing stage.