Christian Panis

DODT: Increasing requirements formalism using domain ontologies for improved embedded systems development

In times of ever-growing system complexity and thus increasing possibilities for errors, high-quality requirements are crucial to prevent design errors in later project phases and to facilitate design verification and validation. To ensure and improve the consistency, completeness and correctness of requirements, formal languages have been introduced as an alternative to using natural language (NL) requirement descriptions. However, in many cases existing NL requirements must be taken into account. The formalization of those requirements by now is a primarily manual task, which therefore is both cumbersome and error-prone. We introduce the tool DODT that semi-automatically transforms NL requirements into semi-formal boilerplate requirements. The transformation builds upon a domain ontology (DO) containing knowledge of the problem domain and upon natural language processing techniques. The tool strongly reduced the required manual effort for the transformation. In addition the quality of the requirements was improved.

XDSPCORE: a compiler-based configurable digital signal processor

XDSPCORE is a digital signal processor (DSP) architecture that enables time- and space-efficient execution of typical digital signal applications written in high-level languages. Our evaluation shows that the corresponding compiler can use all the DSP features as efficiently as a programmer coding in assembly language.

DSPxPlore: design space exploration methodology for an embedded DSP core

High mask and production costs for the newest CMOS silicon technologies increase the pressure to develop hardware platforms useable for different applications or variants of the same application. To provide flexibility for these platforms the need on software programmable embedded processors is increasing. To close the gap concerning consumed silicon area and power dissipation between optimized hardware implementations and software based solutions, it is necessary to adapt the subsystem of the embedded processor to application specific requirements. DSPxPlore can be used to explore the design space of RISC based embedded core architectures. At an early stage of the project the main architectural requirements of the application code can be identified in order to meet the area and power dissipation requirements. During the development process DSPxPlore supports fine-tuning of the subsystem architecture (e.g. modifications of the binary coding of instructions). DSPxPlore is part of a development project for a configurable DSP core.

FSEL - selective predicated execution for a configurable DSP core

Increasing system complexity of SOC applications leads to an increased need for powerful embedded DSP processors. To fulfill the required computational bandwidth, state-of-the-art DSP processors allow executing several instructions in parallel and for reaching higher clock frequencies, they increase the number of pipeline stages. However, deeply pipelined processors have drawbacks in the execution of branch instructions: branch delays. In average, not more than two branch delay slots can be used, additional ones keep unused and decrease the overall system performance. Instead of compensating the drawback of branch delays (e.g. branch prediction circuits), it is possible to reduce the number of branch instructions. Predicated execution (also guarded execution or conditional execution) can be used for implementing if-then-else constructs without using branch instructions. The drawback of traditional predicated execution is decreased code density. This paper introduces selective predicated execution based on FSEL which allows reducing the number of branch instructions without decreasing code density. Selective predicated execution based on FSEL is part of a project for a configurable DSP core.

Extensible and Configurable Processors for System-on-Chip Design

Extensible, configurable, and reconfigurable processor cores mark the start of a new epoch for microprocessors, more suited to SoC design. In this chapter, we present four approaches to achieve higher levels of application-specific performance. Acceleration of a baseline RISC core with a reconfigurable co-processor can provide high performance with a very small amount of configuration data. VLIW DSP approach supporting efficient compiler technology provides a straightforward path for design space exploration and implementation from high-level language entry. An extensible RISC core provides application performance by incorporating new instruction into the instruction set, and finally, a run-time reconfigurable RISC core integrates the application-specific logic into the processor pipeline as a reconfigurable picoGA array

xLIW - a scaleable long instruction word [DSP applications]

Increasing system complexity of SOC applications leads to an increasing requirement of powerful embedded DSP processors. To increase the computational power of DSP processors, the number of pipeline stages has been increased for higher frequencies and the number of parallel executed instructions, to increase the computational bandwidth. To program the parallel units, the VLIW (very long instruction word) has been introduced. Programming the parallel units at the same time leads to an expanded program memory port or to the limitation that only a few units can be used in parallel. To overcome this limitation, this paper proposes a scaleable long instruction word (xLIW). The xLIW concept allows the full usage of the available units in parallel with optimal code density. An instruction buffer included reduces the power dissipation at the program memory ports during loop handling. The xLIW concept is part of a development project of a configurable DSP.

A scaleable instruction buffer for a configurable DSP core

Increasing system complexity of SOC applications leads to an increasing requirement on powerful embedded DSP processors. To increase the performance of DSP processors the number of parallel-executed instructions has been increased. To program the parallel units VLIW (very long instruction word) has been introduced. Traditional VLIW architectures feature poor code density and therefore high area consumption caused by the program memory. To overcome this limitation the proposed configuration DSP core supports unaligned program memory, to reduce the size of the program memory port an execution bundle can be mapped onto several fetch bundles. To overcome the memory bandwidth mismatch between fetch and execution bundle an instruction buffer is introduced. Using the instruction buffer during execution of the inner loops the power dissipation of the DSP subsystems can be reduced. Cache logic is used to control the entries of the instruction buffer during out-of-order execution. This paper describes the architecture and the implementation of the instruction buffer. The instruction buffer is part of a project for a configurable DSP core.

Physical realization oriented area-power-delay tradeoff exploration

High level design-space exploration methodologies focus on optimizations on application and architectural abstraction layer. For power, leakage, and cost sensitive, as well as for performance critical SoC building blocks like embedded domain-specific processors and application specific accelerators, parasitic physical realization effects strongly influence the actual architecture efficiency. The tradeoff between architectural choices and physical implementation consequences needs to be considered to optimize area-power-performance efficiency. In this paper a semi-automated methodology is described that supports architectural optimizations with quantitative feedback on physical realizations already in an early design-space exploration phase. The presented methodology accounts for parasitic effects at the physical realization level, enables an efficient quantitative implementation tradeoff exploration for the design of high-performance SoC building blocks, and provides the foundation for a directed optimization throughout the design process.

Scaleable shadow stack for a configurable DSP concept

SoC (System-on-Chip) applications map complex system functions on a single die. The increasing importance of flexibility in SoC applications leads to raising portion implemented in firmware. Therefore, the demand on computational power of the embedded processors in the application is increasing. The newest silicon technologies (e.g. 0.13 /spl mu/m and lower) help to increase the reachable frequency, but the demand cannot be sufficiently satisfied. One approach to increase the processor frequency is the introduction of pipelining. To guarantee data consistency in deep pipelined processors different methods have been developed. Additional complexity is introduced by the occurrence of interrupts. This paper describes a concept to enable data consistency between the instructions of different pipeline stages in pipelined DSP kernels during interrupt service routines, without the interaction of the DSP itself and with no restrictions concerning the nesting level of the interrupts. The scaleable shadow stack is part of a development project for a configurable DSP concept.