Christian Siemers

Robust partitioning for reliable real-time systems

Summary form only given. Mechatronic systems request for high reliability, especially in the context of time where mostly hard real-time capabilities are mandatory. May be even stronger requirements regard the robustness against software failures and interdependences from erroneous tasks to others. We propose the concept of robust partitioning for reliable real-time embedded systems. The concept consists of two parts, memory space protection and time protection. Memory protection is realized by already existing hardware and software mechanisms. For realizing temporal protection, a two-step timer interrupt system realizing an imprecise computation concept is proposed: if the execution of a module exceeds a certain time limit before the deadline, the first timer interrupt is triggered and a backup routine is started to produce an imprecise result in the remaining time until the second timer expires. This time protection concept shows significant advantages as compared to classical approaches for single, parallel and distributed systems. We give an extended introduction into the concept and discussed first attempts for its realization.

Definition of a Configurable Architecture for Implementation of Global Cellular Automaton

The realisation of Global Cellular Automaton (GCA) using a comparatively high number of communicating finite state machines (FSM) leads to high communication effort. Inside configurable architectures, fixed numbers of FSM and fixed bus widths result in a granularity that makes mapping of larger GCA to these architectures even more difficult. This approach presents a configurable architecture to support mapping of GCA into a single Boolean network to omit increasing communication effort and to receive scalability as well as high efficiency.

Reliable event-triggered systems for mechatronic applications

Mechatronic systems most often require hard real-time behaviour of the controlling system. The standard solution for this kind of application is based on the time-triggered approach, and for certain circumstances the schedulability is provable. In contrast, this paper introduces an approach using some hardware enhancements that allow first to substitute the time-triggered system by an event-triggered system but conserving the reliability, second to enhance the event-triggered system by a two-level reaction system while conserving the hard real-time capabilities and third to combine tasks to improve even the worst-case behaviour. This results in a hard-time-but-weak-logic reaction system when computing time is tide but maintains full processing capabilities and therefore exact reaction values for all reactions whenever possible. This meets the goal of creating an event-triggered and reliable system approach. Combining two or more events to more than one combination will improve the theoretical schedulability of the system too, especially in the case when configurable computing elements are used.

The Universal Configurable Block/Machine—An Approach for a Configurable SoC-Architecture

The universal configurable block/machine is a block-based approach for a configurable system-on-chip-(CSoC-) architecture. The programming model of the blocks is similar to microprocessor models, while the execution model supports configurable computing including reconfiguration. This is achieved by the microarchitecture of the blocks and an additional translation phase, resulting in three phases of overall program execution: fetching, translation and execution. These phases may act without strict coupling, simplifying the duplication of the executing part. The resulting hardware model is classified by four parameter: number of blocks, hyperblock sequencer, hyperblock scheduler and a set of block interconnections. The scheduler indicates that the model is capable of executing operating system work by scheduling hardware resources to threads or processes. This homogeneous CSoC may be used as compile-time defined inhomogeneous application-specific architecture. In this case the development process defines threads to run completely in one or more blocks solving partial problems and communicating to others. This enhances the flexibility and the optimization capabilities towards performance and/or real-time behavior.

Supporting the hard real-time requirements of mechatronic systems by 2-level interrupt service management

Mechatronic systems often require hard real-time behaviour of the controlling system. The standard solution for this kind of application is based on the time-triggered approach, and for certain circumstances the schedulability is provable. In contrast to this, the approach in this paper introduces some hardware enhancements that allow first to substitute the time-triggered system by an event-triggered system and second to enhance the event-triggered system by a two-level reaction system while conserving the hard real-time capabilities. This results in a hard-time-but-weak-logic reaction system when computing time is tide but maintains full processing capabilities and therefore exact reaction values for all reactions whenever possible. Combining two or more events will improve the theoretical schedulability of the system too.

Reconfigurable RISC - A New Approach for Space-Efficient Superscalar Microprocessor Architecture

This approach modifies a RISC processor by integrating an additional Fetch Look-Aside Buffer (FLAB) for instructions. While the first fetch of any instruction results in normal execution, this instruction is combined in parallel with former instructions for later execution and saved inside the FLAB. The architecture works like a dynamic Very-Long-Instruction-Word architecture using code morphing. Extensive simulations indicate that this approach results in average instructions per cycle rate up to 1.4. The more important fact is that these values are obtained at moderate hardware extensions. The Space-Time-Efficiency E is defined and shows values from 0.5 to 1 for all modified architectures, relative to the RISC processor.

Reconfigurable Computing between Classifications and Metrics - The Approach of Space/Time-Scheduling

Reconfigurable computing receives its merits from scheduling time-based into space-based execution. This paper reviews some common parameters and introduces an additional metric for eventhandling. The focus is set on event-bound applications, and a novel architecture is introduced enabling runtime scheduling between time-based and space-based execution.

Modelling programmable logic devices and reconfigurable, microprocessor-related architectures

This paper introduces two basic models for describing the space efficiency and the throughput of configurable devices. The first model focuses on available programmable logic devices (PLD) and shows the relationships of silicon space and computing time to the block size. This model is further subdivided into a particular one for complex PLDs (CPLD) and one for field-programmable gate arrays (FPGA) due to the fact that both incorporate different implementations of programmable logic. The second model was developed to describe the behaviour of block-based, reconfigurable architectures like the recently introduced universal configurable block (UCB) system with respect to block sizes. All models show a specific behaviour concerning the needed silicon area and the data throughput. Consequently these models are useful to determine optimum values for block sizes in different logic architectures.