Christian Sparka

HVM capabilities of CPE run-to-run overlay control

With the introduction of N2x and N1x process nodes, leading-edge factories are facing challenging demands of shrinking design margins. Previously un-corrected high-order signatures, and un-compensated temporal changes of high-order signatures, carry an important potential for improvement of on-product overlay (OPO). Until recently, static corrections per exposure (CPE), applied separately from the main APC correction, have been the industry’s standard for critical layers [1], [2]. This static correction is setup once per device and layer and then updated periodically or when a machine change point generates a new overlay signature. This is a non-ideal setup for two reasons. First, any drift or sudden shift in tool signature between two CPE update periods can cause worse OPO and a higher rework rate, or, even worse, lead to yield loss at end of line. Second, these corrections are made from full map measurements that can be in excess of 1,000 measurements per wafer [3]. Advanced overlay control algorithms utilizing Run-to-Run (R2R) CPE can be used to reduce the overlay signatures on product in High Volume Manufacturing (HVM) environments. In this paper, we demonstrate the results of a R2R CPE control scheme in HVM. The authors show an improvement up to 20% OPO Mean+3Sigma values on several critical immersion layers at the 28nm and 14 nm technology nodes, and a reduction of out-of-spec residual points per wafer (validated on full map). These results are attained by closely tracking process tool signature changes by means of APC, and with an affordable metrology load which is significantly smaller than full wafer measurements.

Overlay mark optimization using the KTD signal simulation system.

As the overlay performance and accuracy requirements become tighter, the impact of process parameters on the target signal becomes more significant. Traditionally, in order to choose the optimum overlay target, several candidates are placed in the kerf area. The candidate targets are tested under different process conditions, before the target to be used in mass production is selected. The varieties of targets are left on the mass production mask and although they will not be used for overlay measurements they still consume kerf real estate. To improve the efficiency of the process we are proposing the KTD (KLA-Tencor Target Designer). It is an easy to use system that enables the user to select the optimum target based on advanced signal simulation. Implementing the KTD in production is expected to save 30% of kerf real estate due to more efficient target design process as well as reduced engineering time. In this work we demonstrate the capability of the KTD to simulate the Archer signal in the context of advanced DRAM processes. For several stacks we are comparing simulated target signals with the Archer100 signals. We demonstrate the robustness feature in the KTD application that enables the user to test the target sensitivity to process changes. The results indicate the benefit of using KTD in the target optimization process.

Automated overlay recipe setup in high-volume manufacturing: improving performance, efficiency, and robustness

As the semiconductor industry continues to drive toward smaller design nodes, overlay error budgets will continue to shrink making metrology ever more challenging. Moreover, this challenge is compounded by the need to continue to drive down costs and increase productivity, especially given the competitive and macro-economic landscape going forward. In order to satisfy these two contradicting requirements, new ways of maintaining metrology tools and recipes are needed. Traditionally, recipes are generated manually by operators or even metrology engineers, involving both tool time and engineering resources. Furthermore, the influence of individual skill levels can lead to undesirable variations and is a potential source of errors that could result in yield loss. By means of automatic recipe generation both engineering and capital equipment resources can be minimized. Implementation of an automated recipe creation process will also result in improved recipe integrity. In this study, we show a methodology of a highly automated recipe generation for overlay measurements. We will outline the benefits of such an implementation and comment on the value for all segments of the semiconductor industry as well as provide data from production fabs demonstrating these capabilities and benefits.

CPE run-to-run overlay control for High Volume Manufacturing

With the introduction of Nix process nodes, leading-edge factories are facing challenging demands in shrinking design margins. Previously uncorrected high-order signatures, and uncompensated temporal changes of high-order signatures, carry an important potential for improvement of on-product overlay (OPO). Until recently, static corrections per exposure (CPE), applied separately from the main APC correction, have been the industrys standard for critical layers [1], [2]. This static correction is setup once per device and layer and then updated periodically or when a machine change point generates a new overlay signature. This is a non-ideal setup for two reasons. First, any drift or sudden shift in tool signature between two CPE update periods can cause worse OPO and a higher rework rate, or, even worse, lead to yield loss at end of line. Second, these corrections are made from full map measurements that can be in excess of 1,000 measurements per wafer [3]. Advanced overlay control algorithms utilizing Run-to-Run (R2R) CPE can be used to reduce the overlay signatures on product in High Volume Manufacturing (HVM) environments. In this paper, we demonstrate the results of a R2R CPE control scheme in HVM. The authors show an improvement up to 20% OPO Mean+3Sigma values on several critical immersion layers at the 28nm and 14 nm technology nodes, and a reduction of out-of-spec residual points per wafer (validated on full map). These results are attained by closely tracking process tool signature changes by means of APC, and with an affordable metrology load which is significantly smaller than full wafer measurements.

In-line focus monitoring and fast determination of best focus using scatterometry

Persistently shrinking design rules and increasing process complexity require tight control and monitoring of the exposure tool parameters [1, 2]. While control of exposure dose by means of resist single metric measurements is common and widely adopted. Focus assessment and monitoring are usually more difficult to achieve. A diffused method to determine process specific dose and focus conditions is based on plotting Bossung curves from single CD-SEM measurements and choosing the best focus setting to obtain the desired target CD with the widest useful window. With this approach there is no opportunity to build a data flow architecture that can enable continuous focus monitoring on nominal production wafers [3-5]. KLA-Tencor has developed a method to enable in-line monitoring of scanner focus on production wafers by measuring resist profile shapes on grating targets using scatterometry, and analyzing the information using AcuShapeTM and K-T AnalyzerTM software. This methodology is based on a fast and robust determination of best scanner focus by analyzing focus-exposure matrices (FEMs). This paper will demonstrate the KT CDFE and FEM Analysis methods and their application in production environment.

Lithography rework reduction and improved process control using AIM targets on aluminum layers in the high-volume production of 110-nm DRAM devices

AIM grating targets were optimized and implemented on the metal 2 Aluminum layer in high volume production of 110-nm DRAM devices. Grating target structures are intrinsically more compatible with Aluminum process design rules, allowing overlay target optimization to better fit the process and better cope with the large grain structure of the Aluminum layer. With the implementation of AIM overlay targets we were able to achieve tighter control of the Aluminum patterning, we also achieved smaller overlay residuals, better matching between post litho and post etch measurements, better modeling and less rework. Above all, AIM targets improve the overlay metrology tool capability and provide a better tool-to-tool matching performance.