Christian Wicpalek

Multi-stage Pulse Shrinking Time-to-Digital Converter for Time Interval Measurements

This paper presents a new structure of Pulse Shrinking Time-to-Digital Converter (TDC) with 20 ps resolution which is implemented in Infineon 0.13 mum CMOS technology. The new interpolating multi-stage TDC with feedback loop and high speed counter accelerates the digitization of the input time interval and is appropriate as Phase Detector for Phase Locked Loop application. The interpolated multi-stage structure efficiently saves the chip area and power consumption. Its Full-Scale-Range (FSR) is about 5000 ps and its differential linearity errors are less than 0.52 LSB.

Novel Digital Front End Based Interference Detection Methods

The concept of Cognitive Radio (CR) is based on detecting the environmental radio spectrum, sensing changes and responding/reacting accordingly. Environmental observation requires methods for interference detection and evaluating the current spectral allocation. It is shown that classical methods of spectrum analysis like the Fast Fourier Transformation (FFT) have critical shortcomings in fullfilling the requirements of CR. The pivotal focus of this paper is to propose alternative approaches suitable for integration into the Digital Front End (DFE) of the Users Equipment (UE).

Analysis of a Two-Bit Frequency Discriminator in an All Digital Phase Locked Loop for RF-Modulation and RF-Frequency Synthesis

A key issue in pushing the digitization of phase locked loops (PLLs) for RF transmitters is the realization of proper phase/frequency detectors in the digital domain. This paper presents a simulative analysis of the properties for and requirements of a two-bit frequency discriminator used for digitization of frequency in all digital PLLs (ADPLLs) with two-point modulation. Effects due to reference clock jitter in one-bit and two-bit frequency discriminators are treated. Furthermore, measurement results for the synthesis mode of the ADPLL used in multi-mode capable terminal are given

System Considerations for a Combined UMTS/GNSS Receiver

This paper introduces a hybrid receiver architecture for user equipment positioning by using UMTS and GNSS signals. After a review of the UMTS and Galileo/GPS signal structures and the state-of-the-art in receiver RF and base-band architectures, a configurable GNSS/UMTS architecture is proposed. The investigated concept is based on a reconfigurable receive chain to prevent duplication of hardware, which will result in considerably lower costs. The biggest challenge in the design of Galileo receivers are the extremely tight noise figure (NF) requirements. Another key issue of integrated GNSS/UMTS receivers is the maximum tolerable UMTS transmit leakage injected into the Galileo receiver.

System Design of a Configurable Highly Digital UMTS/NAVSAT RF-Receiver

This paper introduces a combined UMTS/NAVSAT receiver architecture with one common reconfigurable radio frequency (RF) front-end. After a review of the state-of-the-art for UMTS and NAVSAT receivers, a configurable UMTS/-NAVSAT architecture is proposed. The investigated concept is based on a digital-front-end (DFE) to prevent duplication of hardware, which will result in considerably lower costs. The integration of digital signal processing block into the RFIC is further favored by the advent of RF-CMOS as mainstream technology for RFICs, due to the availability of high speed and low power digital logic blocks. The DFE includes highly reconfigurable filter structures, which enable channel selection for different signal bandwidths according to the configured mode. The analog to digital conversion is carried out with a high dynamic-range/low-power DeltaSigma-analog-to-digital-converter (ADC). This simplifies the design of the analog anti-aliasing filter considerably

Analysis of Spurious Emission and In-Band Phase Noise of an All Digital Phase Locked Loop for RF Synthesis using a Frequency Discriminator

In almost every wireless RF application, a phase locked loop (PLL) is required. Digital signal processing especially for PLLs in CMOS technology is increasingly used instead of conventional analog processing to improve reliability, to reduce power consumption, and to allow for re-configurability. This paper presents a simulative analysis of an all digital PLL (ADPLL) with a two bit frequency discriminator (FD) in the feedback path. Effects on the in-band noise performance due to the sampling rate are treated. Furthermore, a theoretical prediction and simulative analysis of spurious emission offset frequencies will be given.

Digitally controlled oscillator gain estimation for RF-DPLLs in 4G LTE polar transmitters

The gain of a digitally controlled oscillator (DCO) represents a crucial parameter for wideband phase modulators utilized in polar transmitters supporting SC-FDMA in LTE uplink. Accurate normalization of the DCO gain is necessary for a two-point modulation of a RF digital phase-locked loop (DPLL) to not degrade the in-band modulation quality and out-of-band emissions. The DCO gain can change due to process, voltage and temperature effects and therefore has to be estimated during runtime. A common way to estimate the DCO gain is by minimizing the residual error due to phase modulation signal content present in the error feedback signal of the DPLL control loop. This paper derives a simple discrete time, single-rate model of the DCO gain estimation and investigates the behavior and impact on modulation quality for different resource block (RB) allocation scenarios found in LTE uplink transmission. It is shown that the DCO gain estimation is sensitive to modulation signals with contiguous, sparse RB allocation and problems may arise in certain transmission scenarios.

An overall gain estimation algorithm for all digital phase locked loops

Fully digital frequency synthesizers are increasingly used in radio frequency (RF) transceivers. The estimation and calibration of the gain for digital controlled oscillator (DCO) and time-to-digital converter (TDC) which is subject to process, voltage and temperature (PVT) variations are important area of research since they can increase the performance and reduce the complexity of the all digital phase locked loops (ADPLL). Normally these two calibration algorithms are implemented separately. In this paper, an overall gain (including DCO gain and TDC gain) tracking algorithm for an ADPLL is presented. The algorithm is based on correlation analysis used in system identification to estimate the unknown impulse response from DCO input to TDC output by applying a training signal. The result shows that with a sufficiently long training sequence, the accuracy of the estimation result will be within a very fine resolution.

On the Design of a Highly Digital Multimode UMTS/GNSS Receiver

This paper introduces a combined UMTS/GNSS receiver architecture with a single reconfigurable radio frequency (RF) front-end. After a review of the state-of-the-art for UMTS and NAVSAT receivers, a configurable UMTS/-GNSS architecture is proposed. The investigated concept is based on a digital-front-end (DFE) to prevent duplication of hardware, which will result in considerably lower costs. The DFE includes highly reconfigurable filter structures, which enable channel selection for different signal bandwidths according to the configured mode. This decreases the requirements for the analog part because channelization and for GNSS the down conversion to base band are shifted from the analog into the digital domain. The simulation results the considerable performance for a combined UMTS/GNSS receiver using the proposed receiver architecture.